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| exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xrt75r12d twelve channel e3/ds3/sts-1 line interface unit with sonet december 2006 rev. 1.0.1 general description the xrt75r12d is a twelve channel fully integrated line interface unit (liu) featuring exar?s r 3 technology (reconfigurable, relayless redundancy) for e3/ds3/sts-1 applications. the liu incorporates 12 independent receivers, transmitters and jitter attenuators in a single 420 lead tbga package. each channel of the xrt75r12d can be independently configured to operate in e3 (34.368 mhz), ds3 (44.736 mhz) or sts-1 (51.84 mhz). each transmitter can be turned off and tri-stated for redundancy support or for conserving power. the xrt75r12d?s differential receiver provides high noise interference margin and is able to receive data over 1000 feet of cable or with up to 12 db of cable attenuation. the xrt75r12d incorporates an advanced crystal- less jitter attenuator per channel that can be selected either in the transmit or receive path. the jitter attenuator performance meets the etsi tbr-24 and bellcore gr-499 specifications. also, the jitter attenuators can be used for clock smoothing in sonet sts-1 to ds-3 de-mapping. the xrt75r12d provides a parallel microprocessor interface for programming and control. the xrt75r12d supports analog, remote and digital loop-backs. the device al so has a built-in pseudo random binary sequence (prbs) generator and detector with the ability to insert and detect single bit error for diagnostic purposes. applications ? e3/ds3 access equipment ? dslams ? digital cross connect systems ? csu/dsu equipment ? routers ? fiber optic terminals f igure 1. b lock d iagram of the xrt 75r12d ordering information p art n umber p ackage o perating t emperature r ange xrt75r12dib 420 lead tbga -40 c to +85 c xrt75r12d xrt75r12d channel 11 channel 0 channel n... device monitor mtip_n mring_n dmo_n timing control tx pulse shaping hdb3/ b3zs encoder tx control jitter attenuator mux line driver remote loopback hdb3/ b3zs decoder mux agc/ equalizer peak detector los detector slicer jitter attenuator processor interface local loopback clock & data recovery clock synthesizer rd wr addr[7:0] cs int d[7:0] txon txclk_n txpos_n txneg_n rxclk_n rxpos_n rxneg/lcv_n rlos_n rlol_n rtip_n rring_n ttip_n tring_n clkout_n sfm_en e3clk ds3clk sts-clk/12m ict pmode rdy pclk reset
xrt75r12d 2 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 features receiver ? r 3 technology (reconfigurable, relayless redundancy) ? on chip clock and data re covery circuit for high input jitter tolerance ? meets e3/ds3/sts-1 jitter tolerance requirement ? detects and clears los as per g.775 ? receiver monitor mode handles up to 20 db flat loss with 6 db cable attenuation ? on chip b3zs/hdb3 encoder and decoder that can be either enabled or disabled ? on-chip clock synthesizer provides the appropriate rate clock from a si ngle 12.288 mhz clock ? provides low jitter output clock transmitter ? r 3 technology (reconfigurable, relayless redundancy) ? compliant with bellcore gr-499, gr-253 and ansi t1.102 specification for transmit pulse ? tri-state transmit output capability for redundancy applications ? each transmitter can be independently turned on or off ? transmitters provide voltage output drive jitter attenuator ? on chip advanced crystal- less jitter attenuator for each channel ? jitter attenuator can be selected in receive, transmit path, or disabled ? meets etsi tbr 24 jitter transfer requirements ? compliant with jit ter transfer temp late outlined in itu g.751, g.752, g.755 and gr-499-core,1995 standards ? 16 or 32 bits selectable fifo size control and diagnostics ? parallel microprocessor interface for control and configuration ? supports optional internal transmit driver monitoring ? each channel supports analog, remote and digital loop-backs ? single 3.3 v 5% power supply ? 5 v tolerant digital inputs ? available in 420 pin tbga thermally enhanced package ? - 40c to 85c industrial temperature range transmit interface characteristics ? accepts either single-rail or dual-rail data from terminal equipment and generates a bipolar signal to the line ? integrated pulse shaping circuit ? built-in b3zs/hdb3 encoder (which can be disabled) ? accepts transmit clock with duty cycle of 30%- 70% ? generates pulses that comply with the itu-t g.703 pulse template for e3 applications ? generates pulses that comply with the dsx-3 pulse template, as specifie d in bellcore gr-499 -core and ansi t1.102_1993 ? generates pulses that comply with the stsx-1 pulse template, as spec ified in bellcore gr-253- core ? transmitter can be turned off in order to support redundancy designs receive interface characteristics ? integrated adaptive receive equalization (optional) for optimal clock and data recovery ? declares and clears the los defect per itu-t g.775 requirements for e3 and ds3 applications ? meets jitter tolerance requirements, as specified in itu-t g.823_1993 for e3 applications ? meets jitter tolerance requirements, as specified in bellcore gr-499-cor e for ds3 applications ? declares loss of lock (lol) alarm ? built-in b3zs/hdb3 decoder (which can be disabled) ? recovered data can be muted while the los condition is declared ? outputs either single-rail or dual-rail data to the terminal equipment xrt75r12d i rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer table of contents general description............................................................................................................ .. 1 a pplications ............................................................................................................................... ................................ 1 f igure 1. b lock d iagram of the xrt 75r12d.................................................................................................................... .............. 1 ordering information ........................................................................................................... ......... 1 f eatures ............................................................................................................................... ...................................... 2 t ransmit i nterface c haracteristics ....................................................................................................................... 2 r eceive i nterface c haracteristics ......................................................................................................................... 2 pin descriptions (by function) ........................................................................................... 3 s ystem -s ide t ransmit i nput and t ransmit c ontrol p ins ....................................................................................... 3 s ystem -s ide r eceive o utput and r eceive c ontrol p ins ....................................................................................... 6 r eceive l ine s ide p ins ............................................................................................................................... ................ 8 c lock i nterface ............................................................................................................................... .......................... 9 g eneral c ontrol p ins ............................................................................................................................... ............. 10 p ower s upply p ins ............................................................................................................................... ................... 12 g round p ins ............................................................................................................................... .............................. 13 t able 1: l ist by p in n umber ............................................................................................................................... .............................. 14 functional description .... .......................................... ........................................... ............. 18 1.0 r3 technology (reconfigurable, re layless redundancy) ....... ............. ............. ...... 18 1.1 network architecture ...... .............. .............. .............. .............. .............. .............. .......... ..................... 18 f igure 2. n etwork r edundancy a rchitecture .............................................................................................................................. 1 8 2.0 clock synthesizer ....................................................................................................... ................ 19 f igure 3. s implified b lock d iagram of the i nput c lock c ircuitry d riving the m icroprocessor ............................................ 19 t able 2: r eference c lock p erformance s pecifications .............................................................................................................. 19 2.1 clock distribution ...................................................................................................... ........................... 20 f igure 4. c lock d istribution c ongifured in e3 m ode w ithout u sing sfm ................................................................................ 20 3.0 the receiver section .................................................................................................... .............. 21 f igure 5. r eceive p ath b lock d iagram ............................................................................................................................... ........... 21 3.1 receive line interface .................................................................................................. ........................ 21 f igure 6. r eceive l ine i nterface c onnection ............................................................................................................................... .. 21 3.2 adaptive gain control (agc) ............ .............. .............. .............. .............. .............. ........... ................. 21 3.3 receive equalizer ....................................................................................................... ............................ 22 f igure 7. acg/e qualizer b lock d iagram ............................................................................................................................... ........ 22 3.3.1 recommendations for equalizer settings ................................................................................. ............. 22 3.4 clock and data recovery ................................................................................................. .................. 22 3.4.1 data/clock recovery mode ............................................................................................... ............................. 22 3.4.2 training mode.......................................................................................................... .............................................. 22 3.5 los (loss of signal) detector ........................................................................................... ................ 23 3.5.1 ds3/sts-1 los condition ................................................................................................ ..................................... 23 t able 3: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of reqen (ds3 and sts-1 a p - plications ).............................................................................................................................. ............................................ 23 3.5.2 disabling alos/dlos detection .......................................................................................... ........................... 23 3.5.3 e3 los condition:...................................................................................................... ............................................ 23 f igure 8. l oss o f s ignal d efinition for e3 as per itu-t g.775 .................................................................................................. 23 f igure 9. l oss of s ignal d efinition for e3 as per itu-t g.775................................................................................................... 24 3.5.4 interference tolerance................................................................................................. ................................. 24 f igure 10. i nterference m argin t est s et up for ds3/sts-1 ...................................................................................................... 24 f igure 11. i nterference m argin t est s et up for e3. ................................................................................................................... 24 t able 4: i nterference m argin t est r esults ............................................................................................................................... .. 25 3.5.5 muting the recovered data with los condition:.......................................................................... ......... 26 f igure 12. r eceiver d ata output and code violation timing ........................................................................................................ 26 3.6 b3zs/hdb3 decoder ....................................................................................................... ........................... 26 4.0 the transmitter section ................................................................................................. .......... 27 f igure 13. t ransmit p ath b lock d iagram ............................................................................................................................... ....... 27 f igure 14. t ypical interface between terminal equipment and the xrt75r12d ( dual - rail data )............................................ 27 f igure 15. t ransmitter t erminal i nput t iming ............................................................................................................................... 28 f igure 16. s ingle -r ail or nrz d ata f ormat (e ncoder and d ecoder are e nabled ) .................................................................. 28 4.1 transmit clock .......................................................................................................... .............................. 29 4.2 b3zs/hdb3 encoder ....................................................................................................... ........................... 29 4.2.1 b3zs encoding .......................................................................................................... ............................................. 29 f igure 18. b3zs e ncoding f ormat ............................................................................................................................... .................. 29 xrt75r12d ii twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 4.2.2 hdb3 encoding.......................................................................................................... ............................................. 29 f igure 17. d ual -r ail d ata f ormat ( encoder and decoder are disabled ).................................................................................... 29 f igure 19. hdb3 e ncoding f ormat ............................................................................................................................... .................. 30 4.3 transmit pulse shaper ................................................................................................... ...................... 30 f igure 20. t ransmit p ulse s hape t est c ircuit .............................................................................................................................. 3 0 4.3.1 guidelines for using transmit build out circuit ........................................................................ .......... 30 4.4 e3 line side parameters . .............. .............. .............. .............. .............. .............. ............ ....................... 31 f igure 21. p ulse m ask for e3 (34.368 mbits / s ) interface as per itu - t g.703 ............................................................................. 31 t able 5: e3 t ransmitter line side output and receiver line side input specifications .............................................................. 31 f igure 22. b ellcore gr-253 core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications ................................. 32 t able 6: sts-1 p ulse m ask e quations ............................................................................................................................... ............ 32 t able 7: sts-1 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-253)..................................... 33 f igure 23. t ransmit o uput p ulse t emplate for ds3 as per b ellcore gr-499 ......................................................................... 34 t able 8: ds3 p ulse m ask e quations ............................................................................................................................... ................ 34 t able 9: ds3 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-499) ........................................ 35 4.5 transmit drive monitor .................................................................................................. ...................... 36 f igure 24. t ransmit d river m onitor set - up ............................................................................................................................... .... 36 4.6 transmitter section on/off .............................................................................................. ................. 36 5.0 jitter .................................................................................................................. ................................37 5.1 jitter tolerance ........................................................................................................ ............................. 37 f igure 25. j itter t olerance m easurements ............................................................................................................................... ... 37 5.1.1 ds3/sts-1 jitter tolerance requirements ................................................................................ ................ 37 f igure 26. i nput j itter t olerance f or ds3/sts-1 ..................................................................................................................... .38 5.1.2 e3 jitter tolerance requirements ....................................................................................... ....................... 38 f igure 27. i nput j itter t olerance for e3............................................................................................................................ ......... 38 t able 10: j itter a mplitude versus m odulation f requency (j itter t olerance ) ......................................................................... 39 5.2 jitter transfer ......................................................................................................... ............................... 39 t able 11: j itter t ransfer s pecification /r eferences ................................................................................................................... 39 5.3 jitter attenuator ......... .............. .............. .............. .............. .............. .............. .......... ............................ 39 t able 12: j itter t ransfer p ass m asks ............................................................................................................................... ............ 40 f igure 28. j itter t ransfer r equirements and j itter a ttenuator p erformance ...................................................................... 40 5.3.1 jitter generation...................................................................................................... .......................................... 40 6.0 diagnostic features ..................................................................................................... ..............41 6.1 prbs generator and detector ............................................................................................. ............ 41 f igure 29. prbs mode ................................................................................................................ ................................................... 41 6.2 loopbacks .. .............. .............. .............. .............. .............. .............. .............. ........... ................................... 42 6.2.1 analog loopback........................................................................................................ ........................................ 42 f igure 30. a nalog l oopback ............................................................................................................................... ............................ 42 6.2.2 digital loopback ....................................................................................................... .......................................... 43 f igure 31. d igital l oopback ............................................................................................................................... ............................. 43 6.2.3 remote loopback ........................................................................................................ ........................................ 43 f igure 32. r emote l oopback ............................................................................................................................... ............................ 43 6.3 transmit all ones (taos) ................................................................................................ ...................... 44 f igure 33. t ransmit a ll o nes (taos) ........................................................................................................................ .................... 44 7.0 microprocessor interface block .......... ................. ................ ................ ................ .............45 t able 13: s electing the m icroprocessor i nterface m ode .......................................................................................................... 45 f igure 34. s implified b lock d iagram of the m icroprocessor i nterface b lock ........................................................................ 45 7.1 the microprocessor in terface block signals ..... .............. .............. ........... ........... ........... ....... 46 t able 14: xrt75r12d m icroprocessor i nterface s ignals ......................................................................................................... 46 7.2 asynchronous and synchronous description ........ .............. .............. .............. ............... ......... 47 f igure 35. a synchronous p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations .................................. 47 t able 15: a synchronous t iming s pecifications ............................................................................................................................. 48 f igure 36. s ynchronous p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations .................................... 48 t able 16: s ynchronous t iming s pecifications ............................................................................................................................... 49 7.3 register map ............................................................................................................ ................................. 50 t able 17: c ommand r egister a ddress m ap , within the xrt75r12d ........................................................................................... 50 the global/chip-level registers ... .............. .............. .............. .............. .............. ............ ........... ................ 59 t able 18: l ist and a ddress l ocations of g lobal r egisters ........................................................................................................ 59 register description - global registers ........................................................................................ ....... 59 t able 19: aps/r edundancy t ransmit c ontrol r egister - cr0 (a ddress l ocation = 0 x 00) ..................................................... 59 t able 20: aps/r edundancy t ransmit c ontrol r egister - cr8 (a ddress l ocation = 0 x 08) ..................................................... 60 t able 21: c hannel l evel i nterrupt e nable r egister - cr96 (a ddress l ocation = 0 x 60) ......................................................... 61 t able 22: c hannel l evel i nterrupt e nable r egister - cr224 (a ddress l ocation = 0 x e0)....................................................... 62 t able 23: c hannel l evel i nterrupt s tatus r egister - cr97 (a ddress l ocation = 0 x 61) ......................................................... 63 xrt75r12d iii rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 24: c hannel l evel i nterrupt s tatus r egister - cr225 (a ddress l ocation = 0 x e1)....................................................... 64 t able 25: d evice /p art n umber r egister - cr110 (a ddress l ocation = 0 x 6e) ........................................................................... 64 t able 26: c hip r evision n umber r egister - cr111 (a ddress l ocation = 0 x 6f) ......................................................................... 65 the per-channel registers...................................................................................................... ..................... 66 register description - per channel registers ................................................................................... .66 t able 27: xrt75r12d r egister map showing i nterrupt e nable r egisters (ier_ n ) ............................................................... 66 t able 28: s ource l evel i nterrupt e nable r egister - c hannel n a ddress l ocation = 0 xm 1 .................................................... 67 t able 29: xrt75r12d r egister map showing a larm s tatus r egisters (as_ n )........................................................................ 69 t able 30: xrt75r12 r egister map showing a larm s tatus r egisters (as_ n ) .......................................................................... 71 t able 31: xrt75r12d r egister map showing t ransmit c ontrol r egisters (tc_ n ) ................................................................ 75 t able 32: xrt75r12d r egister map showing r eceive c ontrol r egisters (rc_ n ).................................................................. 77 t able 33: xrt75r12d r egister map showing c hannel c ontrol r egisters (cc_ n )................................................................. 79 t able 34: xrt75r12d r egister map showing j itter a ttenuator c ontrol r egisters (ja_ n )................................................. 81 t able 35: xrt75r12d r egister map showing e rror c ounter msb yte r egisters (em_ n ) ..................................................... 82 t able 36: e rror c ounter msb yte r egister - c hannel n a ddress l ocation = 0 xm a................................................................. 83 t able 37: xrt75r12d r egister map showing e rror c ounter lsb yte r egisters (el_ n ) ....................................................... 83 t able 38: e rror c ounter lsb yte r egister - c hannel n a ddress l ocation = 0 xm b.................................................................. 84 t able 39: xrt75r12d r egister map showing e rror c ounter h olding r egisters (eh_ n ) ..................................................... 84 t able 40: e rror c ounter h olding r egister - c hannel n a ddress l ocation = 0 xm c ................................................................ 85 8.0 the sonet/sdh de-sync function within the liu ............................................................... 86 8.1 background and detailed information - sonet de-sync applications .. ........... .............. 86 f igure 37. a s imple i llustration of a ds3 signal being mapped into and transported over the sonet n etwork ............... 87 8.2 mapping/de-mapping jitter/wander ........................................................................................ ......... 88 8.2.1 how ds3 data is mapped into sonet ...................................................................................... ....................... 88 f igure 38. a s imple i llustration of the sonet sts-1 f rame ..................................................................................................... 89 f igure 39. a s imple i llustration of the sts-1 f rame s tructure with the toh and the e nvelope c apacity b ytes d esignated 90 f igure 40. t he b yte -f ormat of the toh within an sts-1 f rame ................................................................................................. 91 f igure 41. t he b yte -f ormat of the toh within an sts-1 f rame ................................................................................................. 92 f igure 42. i llustration of the b yte s tructure of the sts-1 spe ............................................................................................. 93 f igure 43. a n i llustration of t elcordia gr-253-core' s r ecommendation on how map ds3 data into an sts-1 spe ......... 94 f igure 44. a s implified "b it -o riented " v ersion of t elcordia gr-253-core' s r ecommendation on how to map ds3 data into an sts-1 spe...................................................................................................................... .................................................... 94 8.2.2 ds3 frequency offsets and the use of the "stuff opportunity" bits ......................................... 95 f igure 45. a s imple i llustration of a ds3 d ata -s tream being m apped into an sts-1 spe, via a pte .................................... 96 f igure 46. a n i llustration of the sts-1 spe traffic that will be generated by the "s ource " pte, when mapping in a ds3 signal that has a bit rate of 44.736m bps + 1 ppm , into an sts-1 signal .................................................................................. 98 f igure 47. a n i llustration of the sts-1 spe traffic that will be generated by the s ource pte, when mapping a ds3 signal that has a bit rate of 44.736m bps - 1 ppm , into an sts-1 signal ................................................................................... 99 8.3 jitter/wander due to pointer adjustments ........ .............. .............. ........... ............ ........... ........ 99 8.3.1 the concept of an sts-1 spe pointer.................................................................................... ..................... 100 f igure 48. a n i llustration of an sts-1 spe straddling across two consecutive sts-1 frames ......................................... 100 f igure 49. t he b it - format of the 16-b it w ord ( consisting of the h1 and h2 bytes ) with the 10 bits , reflecting the location of the j1 byte , designated ............................................................................................................................... ................... 101 f igure 50. t he r elationship between the c ontents of the "p ointer b its " ( e . g ., the 10- bit expression within the h1 and h2 bytes ) and the l ocation of the j1 b yte within the e nvelope c apacity of an sts-1 f rame ................................................ 101 8.3.2 pointer adjustments within the sonet network ........................................................................... ..... 101 8.3.3 causes of pointer adjustments .......................................................................................... ....................... 102 f igure 51. a n i llustration of an sts-1 signal being processed via a s lip b uffer .................................................................. 103 f igure 52. a n i llustration of the b it f ormat within the 16- bit word ( consisting of the h1 and h2 bytes ) with the "i" bits des - ignated ............................................................................................................................... .............................................. 104 f igure 53. a n i llustration of the b it -f ormat within the 16- bit word ( consisting of the h1 and h2 bytes ) with the "d" bits des - ignated ............................................................................................................................... .............................................. 105 8.3.4 why are we talking about pointer adjustments? .......................................................................... ... 106 8.4 clock gapping jitter .................................................................................................... ....................... 106 f igure 54. i llustration of the t ypical a pplications for the liu in a sonet d e -s ync a pplication ...................................... 106 8.5 a review of the category i intrinsic ji tter requirements (per telcordia gr-253-core) for ds3 applications .......................................................................................................... ................ 107 t able 41: s ummary of "c ategory i i ntrinsic j itter r equirement per t elcordia gr-253-core, for ds3 applications ...... 107 8.5.1 ds3 de-mapping jitter.................................................................................................. ..................................... 108 8.5.2 single pointer adjustment .............................................................................................. ............................. 108 f igure 55. i llustration of s ingle p ointer a djustment s cenario ............................................................................................. 108 8.5.3 pointer burst.......................................................................................................... ............................................ 109 f igure 56. i llustration of b urst of p ointer a djustment s cenario ......................................................................................... 109 8.5.4 phase transients....................................................................................................... ........................................ 109 xrt75r12d iv twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 f igure 57. i llustration of "p hase -t ransient " p ointer a djustment s cenario .......................................................................... 110 8.5.5 87-3 pattern........................................................................................................... ............................................... 110 f igure 58. a n i llustration of the 87-3 c ontinuous p ointer a djustment p attern .................................................................. 110 8.5.6 87-3 add ............................................................................................................... .................................................... 111 f igure 59. i llustration of the 87-3 a dd p ointer a djustment p attern ..................................................................................... 111 8.5.7 87-3 cancel............................................................................................................ ................................................ 111 f igure 60. i llustration of 87-3 c ancel p ointer a djustment s cenario .................................................................................... 112 8.5.8 continuous pattern..................................................................................................... .................................... 112 f igure 61. i llustration of c ontinuous p eriodic p ointer a djustment s cenario .................................................................... 112 8.5.9 continuous add ........................................................................................................ ......................................... 113 f igure 62. i llustration of c ontinuous -a dd p ointer a djustment s cenario ............................................................................. 113 8.5.10 continuous cancel..................................................................................................... .................................... 113 f igure 63. i llustration of c ontinuous -c ancel p ointer a djustment s cenario ....................................................................... 114 8.6 a review of the ds3 wander requirements per ansi t1.105.03b-1997. ..... .............. ............. 114 8.7 a review of the intrinsic jitter and wand er capabilities of the liu in a typical system application ................................................................................................................... ........................... 114 8.7.1 intrinsic jitter test results.......................................................................................... .............................. 114 t able 42: s ummary of "c ategory i i ntrinsic j itter t est r esults " for sonet/ds3 a pplications ......................................... 115 8.7.2 wander measurement test results........................................................................................ .................. 116 8.8 designing with the liu .................................................................................................. ....................... 116 8.8.1 how to design and conf igure the liu to permit a system to meet the above-mentioned intrin - sic jitter and wander requirements............................................................................................. .............. 116 f igure 64. i llustration of the liu being connected to a m apper ic for sonet d e -s ync a pplications .............................. 116 c hannel c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 06................................................................... 117 c hannel 1 a ddress l ocation = 0 x 0e .......................................................... 117 c hannel 2 a ddress l ocation = 0 x 16 ........................................................... 117 c hannel c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 06................................................................... 118 c hannel 1 a ddress l ocation = 0 x 0e ............................................................... 118 c hannel 2 a ddress l ocation = 0 x 16 ................................................................. 118 j itter a ttenuator c ontrol r egister - (c hannel 0 a ddress l ocation = 0 x 07................................................. 118 c hannel 1 a ddress l ocation = 0 x 0f.................................................... 118 c hannel 2 a ddress l ocation = 0 x 17 .................................................... 118 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07.................................................. 119 c hannel 1 a ddress l ocation = 0 x 0f.............................................. 119 c hannel 2 a ddress l ocation = 0 x 17 .............................................. 119 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07.................................................. 119 c hannel 1 a ddress l ocation = 0 x 0f............................................. 119 c hannel 2 a ddress l ocation = 0 x 17 ............................................. 119 8.8.2 recommendations on pre-processing the ga pped clocks (from the mapper/asic device) prior to routing this ds3 clock an d data-signals to the transmit inputs of the liu ...................... 119 f igure 65. i llustration of minor pattern p1 .............................................................................................................. ........... 120 f igure 66. i llustration of minor pattern p2 .............................................................................................................. ........... 121 f igure 67. i llustration of p rocedure which is used to s ynthesize major pattern a....................................................... 121 f igure 68. i llustration of minor pattern p3 .............................................................................................................. ........... 122 f igure 69. i llustration of p rocedure which is used to s ynthesize pattern b ................................................................... 122 f igure 70. i llustration of the super pattern which is output via the "oc-n to ds3" m apper ic ................................... 123 f igure 71. s imple i llustration of the liu being used in a sonet d e -s ynchronizer " a pplication ......................................... 123 8.8.3 how does the liu permit the user to comply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)? ........................................................................................... ............... 123 t able 43: m easured aps r ecovery t ime as a function of ds3 ppm offset ............................................................................. 124 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07.................................................. 125 c hannel 1 a ddress l ocation = 0 x 0f............................................. 125 c hannel 2 a ddress l ocation = 0 x 17 ............................................. 125 8.8.4 how should one configure the liu, if on e needs to support "daisy-chain" testing at the end customer's site? ............................................................................................................... .................................... 125 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07.................................................. 125 c hannel 1 a ddress l ocation = 0 x 0f.................................................... 125 c hannel 2 a ddress l ocation = 0 x 17 .................................................... 125 9.0 electrical characteristics .............................................................................................. ....126 t able 44: a bsolute m aximum r atings ............................................................................................................................... ............ 126 t able 45: dc e lectrical c haracteristics :.............................................................................................................................. ..... 126 ordering information........................................................................................................... ......128 p ackage d imensions - ............................................................................................................................. ............... 128 xrt75r12d v rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer r evisions ............................................................................................................................... ................................. 129 xrt75r12d 3 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 pin descriptions ( by function ) system-side transmit input and transmit control pins p in # s ignal n ame t ype d escription p4 txon i transmit on/off input upon power up, the transmitters are powered on. turning the transmitters on or off is selected through the microprocessor interface by programming the appropriate channel register if this pin is pulled "high". if the txon pin is pulled "low", all 12 transmitters are powered off. n ote : txon is ideal for redundancy applications. see the r 3 technology section of this datasheet for more details. internally pulled "high". f22 aa22 h22 y23 g26 aa25 g1 aa2 h5 y4 f5 aa5 txclk0 txclk1 txclk2 txclk3 txclk4 txclk5 txclk6 txclk7 txclk8 txclk9 txclk10 txclk11 i transmit clock input these input pins have three functions: ? they function as the timing source for the transmit section of the corresponding channel within the xrt75r12d. ? they are used by the transmit sect ion of the liu ic to sample the corresponding txpos_n and txneg_n input pins. ? they are used to clock the prbs generator n ote : the user is expected to supply a 44.736mhz 20ppm clock signal (for ds3 applications), 34.368mhz 20 ppm clock signal (for e3 applications) or a 51.84mhz 4.6ppm clock signal (for sts-1, stratum 3e or better applications). e23 ab24 j22 aa23 g25 aa26 g2 aa1 j5 aa4 e4 ab3 txpos0 txpos1 txpos2 txpos3 txpos4 txpos5 txpos6 txpos7 txpos8 txpos9 txpos10 txpos11 i transmit positive data input the function of these digitial input pins depends upon whether the corre - sponding channel has been configured to operate in the single-rail or dual-rail mode. single rail mode - transmit data input operating in the single-rail mode; all transmit input data will be serially applied to this input pin. this signal will be latched into the transmit sec - tion circuitry on the active edge of the txclk_n signal. the transmit section of the liu ic will then encode this data into either the b3zs line code (for ds3 and sts-1 applications) or the hdb3 line code (for e3 applications). dual rail mode - transmit positive data input in the dual-rail mode, the user should apply a pulse to this input pin when a positive-polarity pulse is to be transmitted onto the line. this signal will be latched into the transmit section circuitry upon the active edge of the txclk_n signal,. the transmit section of the liu ic will not encode this data into either the b3zs or hdb3 line codes. if the user configures the liu ic to operate in the dual-rail mode, b3zs/hdb3 encoding must have already been done prior to this input. xrt75r12d 4 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer c25 ab25 h23 w23 h24 y26 h3 y1 h4 w4 c2 ab2 txneg0 txneg1 txneg2 txneg3 txneg4 txneg5 txneg6 txneg7 txneg8 txneg9 txneg10 txneg11 i transmit negative data input when a channel has been configured to operate in the dual-rail mode, the user should apply a pulse to this input pin anytime the transmit section of the liu ic to generate a negative-pola rity pulse onto the line. this signal will be latched into the transmit section circuitry upon the active edge of the txclk_n signal. n ote : in the single-rail mode, this input pin has no function, and should be tied to gnd. b24 ae24 c20 ad20 c16 ad16 c11 ad11 c7 ad7 c3 ad3 ttip0 ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 ttip8 ttip9 ttip10 ttip11 o transmit ttip output - positive polarity signal these output pins along with the co rresponding tring_n output pins, function as the transmit ds3/e3/sts -1 line output signal drivers for a given channel of the xrt75r12d. connect this signal and the corresponding tring_n output signal to a 1:1 transformer. whenever the transmit section of t he channel generates and transmits a positive-polarity pulse onto the line, this output pin will be pulsed to a high ervoltage than its corresponding tring_n output pins. conversely, whenever the transmit se ction of the channel generates and transmit a negative-polarity pulse onto the line, this output pin will be pulsed to a lower voltage than its corresponding tring_n output pin. n ote : this output pin will be tri-stated wh enever the txon input pin or bit- field is set to "0". c24 ad24 b20 ae20 b16 ae16 b11 ae11 b7 ae7 b3 ae3 tring0 tring1 tring2 tring3 tring4 tring5 tring6 tring7 tring8 tring9 tring10 tring11 o transmit ring output - negative polarity signal these output pins along with the co rresponding ttip_n output pins, func - tion as the transmit ds3/e3/sts-1 line output signal drivers for a given channel, within the xrt75r12d. connect this signal and the corresponding ttip_n output signal to a 1:1 transformer. whenever the transmit section of t he channel generates and transmits a positive-polarity pulse onto the line, th is output pin will be pulsed to a lower voltage than its corresponding ttip_n output pin. conversely, whenever the transmit se ction of the channel generates and transmit a negative-polarity pulse onto the line, this output pin will be pulsed to a higher voltage than its corresponding ttip_n output pin. n ote : this output pin will be tri-stated wh enever the txon input pin or bit- field is set to "0". system-side transmit input and transmit control pins p in #s ignal n ame t ype d escription xrt75r12d 5 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 c23 ad23 d19 ac19 d15 ac15 e11 ab11 e8 ab8 c4 ad4 mtip0 mtip1 mtip2 mtip3 mtip4 mtip5 mtip6 mtip7 mtip8 mtip9 mtip10 mtip11 i monitor tip input - positive polarity signal these input pins along with mring_n function as the tr ansmit drive moni - tor output (dmo) in put monitoring pins. (1) to monitor the transmit out - put line signal and (2) to perform this monitoring externally, then this pin must be connected to the corresponding ttip_n output pin via a 270w series resistor. similarly, the mring_n input pin must also be connected to its corresponding tring_n output pin via a 270w series resistor. the mtip_n and mring_n input pins will continuously monitor the trans - mit output line signal via the ttip_n and tring_n output pins for bipolar activity. if these pins do not detect any bipolar activity for 128 bit periods, then the transmit drive monitor circuit will drive the corresponding dmo_n output pin "high" in order to denote a possible fault condition in the trans - mit output line signal path. n ote : these input pins are inactive if the user chooses to internally monitor the transmit output line signal. d23 ac23 e19 ab19 e16 ab16 d10 ac10 d8 ac8 d4 ac4 mring0 mring1 mring2 mring3 mring4 mring5 mring6 mring7 mring8 mring9 mring10 mring11 i monitor ring input these input pins along with mtip_n func tion as the transmit drive monitor output (dmo) input monitoring pins. (1) to monitor the transmit output line signal and (2) to perform this monitoring externally, then this input pin must be connected to the corresponding tring_n output pin via a 270w series resistor. similarly, the mtip_n input pin must be connected to its corresponding ttip_n output pin via a 270w series resistor. the mtip_n and mring_n input pins will continuously monitor the trans - mit output line signal via the ttip_n and tring_n output pins for bipolar activity. if these pins do not detect any bipolar activity for 128 bit periods, then the transmit drive monitor circuit will drive the corresponding dmo_n output pin "high" to indicate a possible fault condition in the transmit out - put line signal path. n ote : these input pins are inactive if the user chooses to internally monitor the transmit output line signal. n3 n4 n5 n1 m1 l2 m2 m3 m4 m5 k2 j1 dmo0 dmo1 dmo2 dmo3 dmo4 dmo5 dmo6 dmo7 dmo8 dmo9 dmo10 dmo11 o drive monitor output these output signals are used to indicate a fault condition within the trans - mit output signal path. this output pin will toggle "high" an ytime the transmit drive monitor cir - cuitry either, via the corresponding mtip and mring input pins or inter - nally, detects no bipolar pulses via the transmit output line signal (e.g., via the ttip_m and tring_m output pins) for 128 bit-periods. this output pin will be driven "low" anytime the transmit drive monitor cir - cuitry has detected at le ast one bipolar pulse via the transmit output line signal within the last 128 bit periods. system-side transmit input and transmit control pins p in #s ignal n ame t ype d escription xrt75r12d 6 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer system-side receive output and receive control pins p in # s ignal n ame t ype d escription d25 ad25 g23 aa24 j24 u24 j3 u3 g4 aa3 d2 ad2 rlos0 rlos1 rlos2 rlos3 rlos4 rlos5 rlos6 rlos7 rlos8 rlos9 rlos10 rlos11 o receive loss of signal output indicator this output pin indicates loss of signal (los) defect condition for the corre - sponding channel. "low" - indicates that the corresponding channel is not currently declaring the los defect condition. "high" - indicates that the corresponding channel is currently declaring the los defect condition. g22 ab26 k22 u22 l24 w25 l3 w2 k5 u5 g5 ab1 rlol0 rlol1 rlol2 rlol3 rlol4 rlol5 rlol6 rlol7 rlol8 rlol9 rlol10 rlol11 o receive loss of lock output indicator this output pin indicates loss of lo ck (lol) condition for the corresponding channel. "low" - indicates that the corresponding channel is not declaring the lol condition. "high" - indicates that the correspondin g channel is currently declaring the lol condition. n ote : the receive section of a given ch annel will declare the lol condition anytime the frequency of the reco vered clock (rclk) signal differs from that of the reference clock pr ogrammed for that channel by 0.5% or more. e25 ad26 g24 y24 l22 t22 l5 t5 g3 y3 e2 ad1 rxpos0 rxpos1 rxpos2 rxpos3 rxpos4 rxpos5 rxpos6 rxpos7 rxpos8 rxpos9 rxpos10 rxpos11 o receive positive data output the function of these output pins depends upon whether the channel has been configured to operate in the si ngle-rail or dual-rail mode. dual-rail mode - receive po sitive polarity data output if the channel has been configured to o perate in the dual-rail mode, then all positive-polarity data will be output via this pin. the negative-polarity data will be output via the corresponding rxneg_n pin. in other words, the receive section of the corresponding channel will pulse this output pin "high" for one period of rclk_n anytime it receives a positive-polarity pulse via the rtip/ rring input pins. the data output via this pin is update d upon the active edge of rxclk_n output clock signal. single-rail mode - receive data output in the single-rail mode, all receive (or recovered) data will be output via this pin. the data output via this pin is update d upon the active edge of rxclk_n output clock signal. xrt75r12d 7 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 f23 ac26 f24 u23 l23 t24 l4 t3 f3 u4 f4 ac1 rxneg/lcv0 rxneg/lcv1 rxneg/lcv2 rxneg/lcv3 rxneg/lcv4 rxneg/lcv5 rxneg/lcv6 rxneg/lcv7 rxneg/lcv8 rxneg/lcv9 rxneg/lcv10 rxneg/lcv11 o receive negative data output/line code violation the function of these pins depends on whether the xrt75r12d is configured in single rail or dual rail mode. dual-rail mode - receive ne gative polarity data output in the dual-rail mode, all negative-polarity data will be output via this pin. the positive-polarity data will be output via th e corresponding rxpo s_n output pin. in other words, the receive section of the corresponding channel will pulse this output pin "high" for one period of rxclk_n anytime it receives a negative- polarity pulse via the rt ip/rring input pins. the data output via this pin is upda ted upon the active edge of the rclk_n output clock signal. single-rail mode - line code violation indicator output in the single-rail mode, this output pin will function as the line code violation indicator output. in this configuration, the receive sect ion of the channel will pulse this output pin "high" for at least one rclk period wh enever it detects either an lcv (line code violation) or an exz (excessive zero event). the data that is output via this pin is updated upon the active edge of the rclk_n output clock signal. e24 ac25 j23 v23 k24 t23 k3 t4 j4 v4 e3 ac2 rxclk0 rxclk1 rxclk2 rxclk3 rxclk4 rxclk5 rxclk6 rxclk7 rxclk8 rxclk9 rxclk10 rxclk11 o receive clock output this output pin functions as the receive or recovered clock signal. all receive (or recovered) data will output via the rxpos_n and rxneg_n outputs upon the active edge of this clock signal. additionally, if the device/channel has been configured to operate in the single- rail mode, then the rneg_n/lcv_n output pins will also be updated upon the active edge of this clock signal. system-side receive output and receive control pins p in #s ignal n ame t ype d escription xrt75r12d 8 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer receive line side pins p in # s ignal n ame t ype d escription b22 ae22 b18 ae18 a14 af14 d13 ac13 b9 ae9 b5 ae5 rtip0 rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 rtip8 rtip9 rtip10 rtip11 i receive tip input these input pins along with the corresponding rring_n input pin function as the receive ds3/e3/sts-1 line input si gnal for a given channel of the xrt75r12d. cconnect this signal and the corres ponding rring_n input signal to a 1:1 transformer. whenever the rtip/rring input pins are receiving a positive-polarity pulse within the incoming ds3, e3 or sts-1 line signal, this input pin will be pulsed to a higher voltage than its corresponding rring_n input pin. conversely, whenever the rtip/rring input pins are receiving a negative- polarity pulse within the incoming ds3, e3 or sts-1 line signal, this input pin will be pulsed to a lower voltage than its corresponding rring_n input pin. c22 ad22 c18 ad18 b14 ae14 c13 ad13 c9 ad9 c5 ad5 rring0 rring1 rring2 rring3 rring4 rring5 rring6 rring7 rring8 rring9 rring10 rring11 i receive ring input these input pins along with the correspondin g rtip_n input pin function as the receive ds3/e3/sts-1 line input si gnal for a given channel of the xrt75r12d. connect this signal and the corresponding rtip_n input signal to a 1:1 trans - former. (see figure 6) whenever the rtip/rring input pins are receiving a positive-polarity pulse within the incoming ds3, e3 or sts-1 li ne signal, then this input pin will be pulsed to a lower voltage than its corresponding rtip_n input pin. conversely, whenever the rtip/rring input pins are receiving a negative- polarity pulse within the incoming ds3, e3 or sts-1 line signal, then this input pin will be pulsed to a higher voltage than its corresponding rtip_n input pin. xrt75r12d 9 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 clock interface p in # s ignal n ame t ype d escription r5 sfm_en i single frequency mode enable this input pin is used to configure the xrt75r12d to operate in the sfm (sin - gle frequency mode). when this feature is invoked, the sfm synthesizer will become active. by applying a 12.288mhz clock signal to t he sts-1clk/12m pin, the xrt75r12d will generate all of the appropriate clock signals (e.g., 34.368mhz, 44.736mhz or 51.84). the xrt75r12d internal circ uitry will route each of these synthe - sized clock signals to the appropriate nodes of the corresponding channels in the xrt75r12d. "low" - disables the single frequency m ode. in this setting, the user is required to supply to the e3clk, ds3clk or sts-1clk input pins all of the rel - evant clock signals that are to be used within the chip. "high" - enables the single-frequency mode. n ote : this input pin is internally pulled low. r1 e3clk i e3 clock input (34.368 mhz 20 ppm) if any one of the channels is configured in e3 mode, a reference clock of 34.368 mhz 20 ppm is applied to this input pin. if the liu is used in e3 mode only, this pin must be connected to the ds3clk input pin to have access to the inter - nal microprocessor. n ote : sfm mode negates the need for this clock t1 ds3clk i ds3 clock input (44.736 mhz 20 ppm) if any one of the channels is configur ed in ds3 mode, a reference clock of 44.736 mhz 20 ppm is applied to this input pin. n ote : sfm mode negates the need for this clock u1 sts-1clk/12m i sts-1 clock input (51.84 mhz 20 ppm) if any one of the channels is configured in sts-1 mode, a reference clock of 51.84mhz 20 ppm is applied to this inpu t pin. if the liu is used in sts-1 mode only, this pin must be connected to the ds3clk input pin to have access to the internal microprocessor. single frequency mode clock input (12.288mhz 20 ppm) in single frequency mode, a reference clock of 12.288 mhz 20 ppm is con - nected to this pin and the internal cl ock synthesizer generates the appropriate clock frequencies based on the configurati on of the rates (e3, ds3 or sts-1). c26 w22 k23 w24 j25 v25 j2 v2 k4 w3 c1 w5 clkout0 clkout1 clkout2 clkout3 clkout4 clkout5 clkout6 clkout7 clkout8 clkout9 clkout10 clkout11 o reference clock out a reference clock pin is provided for eac h channel that will supply a precise data rate frequency derived from either the clock input pin (e3clk, ds3clk, or sts- 1clk) or the 12.288mhz input in sfm mode. this frequency will be as stable as the original source. it is designed to provide the attached framer with its appro - priate reference clock. xrt75r12d 10 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer general control pins p in # s ignal n ame t ype d escription p3 test **** factory test mode input pin this pin must be connected to gnd for normal operation. n ote : this input pin is internally pulled "low". ae25 trst i test reset test boundary scan ab23 tms i test mode select test boundary scan ab5 tck i test clock test boundary scan ab4 tdi i test data input test boundary scan ae2 tdo o test data output test boundary scan microprocessor parallel interface - p in # s ignal n ame t ype d escription j26 pmode i this pin controls the microprocessor parallel interface mode. "high" sets a synchronous clocked interf ace mode with a clock from the host. "low" sets an asynchronous mode where a clock internal to the xrt75r12d will time the operations. p24 pclk i high speed clock supplied by the host to provide timing in the synchronous interface mode. this signal must be a square-wave. n24 cs i chip select input (active low) initiates a read or write operation. when "high", no parallel communication is active between the liu and the host. n22 wr i write input (active low) enables the host to write data d[7:0] into the liu register space at address addr[7:0]. n23 rd i read input (active low) commands the liu to transfer the contents of a register specified by addr[7:0] to the host. n25 rdy o ready line output (active low) provides a handshake between the liu and the host that co mmunicates when an operation has been completed. n ote : this pin must be pulled "high" with a 3k ? 1% resistor. xrt75r12d 11 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 k25 m22 m23 m24 k26 l26 m26 n26 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 i an eight bit direct address bus that specifies the source/destination register for a read or write operation. p22 r26 t26 u26 r25 r24 r23 r22 d0 d1 d2 d3 d4 d5 d6 d7 i/o an eight bit bi-directional data bus that pr ovides the data into the liu for a write operation or the data out to the host for a read operation. p26 int o interrupt active output (active low) normally, this output pin will be pulled "high". however, if the user enables interrupts within the liu, and if those c onditions occur, the xrt75r12d will sig - nal an interrupt from the microprocessor by pulling this output pin "low". the host microprocessor must ascertain the sour ce of the interrupt and service it. reading the source of the inte rupt will clear the flag and the int pin will go back high unless another interrupt has gone active. n otes : 1. this pin will remain "low" until the interrupt has been serviced. 2. this pin must be pulled "high" with a 3k ? 1% resistor. n2 reset i reset input pulsing this input "low" causes the xrt75r12d to reset the contents of the on- chip command registers to their default values. as a consequence, the xrt75r12d will then also be operating in its default condition. for normal operation this input pin should be at a logic "high". n ote : this input pin is internally pulled high. microprocessor parallel interface - p in #s ignal n ame t ype d escription xrt75r12d 12 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer power supply pins p in n ame p in n umbers d escription rvdd0 rvdd1 rvdd2 rvdd3 rvdd4 rvdd5 rvdd6 rvdd7 rvdd8 rvdd9 rvdd10 rvdd11 d22 ac22 d18 ac18 e15 ab15 e12 ab12 a9 af9 d5 ac5 receive analog power supply (3.3v 5%) rvdd should not be shared with other power supplies. it is recommended that rvdd be isolated from the digital power supply dvdd and the analog power supply tvdd. for best results, use an internal power plane for isola - tion. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through an external 0.1 f capacitor. tvdd0 tvdd1 tvdd2 tvdd3 tvdd4 tvdd5 tvdd6 tvdd7 tvdd8 tvdd9 tvdd10 tvdd11 b23 ae23 b19 ae19 b15 ae15 b10 ae10 a6 af6 b4 ae4 transmit analog power supply (3.3v 5%) tvdd can be shared with dvdd. however, it is recommended that tvdd be isolated from the analog power supply rvdd. for best results, use an inter - nal power plane for isolation. if an internal power plane is not available, a fer - rite bead can be used. each power supply pin should be bypassed to ground through an external 0.1 f capacitor. avdd m25, t25, ab21, ab18, af13, af12, ab9, ab6, r4, k1, e6, e9, a12, a13, e18, e21, analog power supply (3.3v 5%) avdd should be isolated from the digital power supplies. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through at least one 0.1 f capacitor. dvdd d26, f25, h25, p25, w26, v24, y22, af21, af20, af17, af16, ad14, ad12, af11, af8, af7, af24 , ad6, af3, y5, v3, w1, p5, p2, h2, f2, d1, c6, a7, a3, a8, a11, c12, c14, a16, a17, a20, a21, a24 digital power supply (3.3v 5%) dvdd should be isolated from the analog power supplies. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. every two dvdd power supply pins should be bypassed to ground through at least one 0.1 f capacitor. xrt75r12d 13 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 ground pins p in n ame p in n umbers d escription rgnd0 rgnd1 rgnd2 rgnd3 rgnd4 rgnd5 rgnd6 rgnd7 rgnd8 rgnd9 rgnd10 rgnd11 a22 af22 a18 af18 e14 ab14 e13 ab13 d9 ac9 a5 af5 receive analog ground it?s recommended that all ground pins of this device be tied together. tgnd0 tgnd1 tgnd2 tgnd3 tgnd4 tgnd5 tgnd6 tgnd7 tgnd8 tgnd9 tgnd10 tgnd11 a23 af23 a19 af19 a15 af15 a10 af10 b6 ae6 a4 af4 transmit analog ground it?s recommended that all ground pins of this device be tied together. agnd a1, a2, a25, a26, b1, b2, b25, b26, c8, c10, c17, c19, c21, d17, d21, e5, e22, l25, u25, ab22, ab20, ab17, ab10, ab7, r3, l1, e7, e10, b12, b13, e17, e20, t2, u2, ac17, ac21, ad8, ad10, ad15, ad17, ad19, ad21, ae1, ae26, ae12, ae13, af1, af2, af25, af26, c15 analog ground it?s recommended that all ground pins of this device be tied together. dgnd e26, f26, h26, p23, , v26, y25, v22, ac24, ac20, ac16, ac14, ac12, ac11, ae8, ae17, ae21, ac7, ac6, ac3, v5, y2, v1, r2, p1, h1, f1, e1, d3, d7, b8, d6, d11, d12, d14, d16, b17, d20, b21, d24 digital ground it?s recommended that all ground pins of this device be tied together. xrt75r12d 14 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 1: l ist by p in n umber p in p in n ame a1 agnd a2 agnd a3 dvdd a4 tgnd10 a5 rgnd10 a6 tvdd8 a7 dvdd a8 dvdd a9 rvdd8 a10 tgnd6 a11 dvdd a12 avdd a13 avdd a14 rtip4 a15 tgnd4 a16 dvdd a17 dvdd a18 rgnd2 a19 tgnd2 a20 dvdd a21 dvdd a22 rgnd0 a23 tgnd0 a24 dvdd a25 agnd a26 agnd b1 agnd b2 agnd b3 tring10 b4 tvdd10 b5 rtip10 b6 tgnd8 b7 tring8 b8 dgnd b9 rtip8 b10 tvdd6 b11 tring6 b12 agnd b13 agnd b14 rring4 b15 tvdd4 b16 tring4 b17 dgnd b18 rtip2 b19 tvdd2 b20 tring2 b21 dgnd b22 rtip0 b23 tvdd0 b24 ttip0 b25 agnd b26 agnd c1 clkout10 c2 txneg10 c3 ttip10 c4 mtip10 c5 rring10 c6 dvdd c7 ttip8 c8 agnd c9 rring8 c10 agnd c11 ttip6 c12 dvdd c13 rring6 c14 dvdd p in p in n ame c15 agnd c16 ttip4 c17 agnd c18 rring2 c19 agnd c20 ttip2 c21 agnd c22 rring0 c23 mtip0 c24 tring0 c25 txneg0 c26 clkout0 d1 dvdd d2 rlos10 d3 dgnd d4 mring10 d5 rvdd10 d6 dgnd d7 dgnd d8 mring8 d9 rgnd8 d10 mring6 d11 dgnd d12 dgnd d13 rtip6 d14 dgnd d15 mtip4 d16 dgnd d17 agnd d18 rvdd2 d19 mtip2 d20 dgnd d21 agnd d22 rvdd0 p in p in n ame d23 mring0 d24 dgnd d25 rlos0 d26 dvdd e1 dgnd e2 rxpos10 e3 rxclk10 e4 txpos10 e5 agnd e6 avdd e7 agnd e8 mtip8 e9 avdd e10 agnd e11 mtip6 e12 rvdd6 e13 rgnd6 e14 rgnd4 e15 rvdd4 e16 mring4 e17 agnd e18 avdd e19 mring2 e20 agnd e21 avdd e22 agnd e23 txpos0 e24 rxclk0 e25 rxpos0 e26 dgnd f1 dgnd f2 dvdd f3 rxneg/lcv8 f4 rxneg/lcv10 p in p in n ame xrt75r12d 15 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 f5 txclk10 f22 txclk0 f23 rxneg/lcv0 f24 rxneg/lcv2 f25 dvdd f26 dgnd g1 txclk6 g2 txpos6 g3 rxpos8 g4 rlos8 g5 rlol10 g22 rlol0 g23 rlos2 g24 rxpos2 g25 txpos4 g26 txclk4 h1 dgnd h2 dvdd h3 txneg6 h4 txneg8 h5 txclk8 h22 txclk2 h23 txneg2 h24 txneg4 h25 dvdd h26 dgnd j1 dmo11 j2 clkout6 j3 rlos6 j4 rxclk8 j5 txpos8 j22 txpos2 j23 rxclk2 j24 rlos4 p in p in n ame j25 clkout4 j26 pmode k1 avdd k2 dmo10 k3 rxclk6 k4 clkout8 k5 rlol8 k22 rlol2 k23 clkout2 k24 rxclk4 k25 addr0 k26 addr4 l1 agnd l2 dmo5 l3 rlol6 l4 rxneg/lcv6 l5 rxpos6 l22 rxpos4 l23 rxneg/lcv4 l24 rlol4 l25 agnd l26 addr5 m1 dmo4 m2 dmo6 m3 dmo7 m4 dmo8 m5 dmo9 m22 addr1 m23 addr2 m24 addr3 m25 avdd m26 addr6 n1 dmo3 n2 reset p in p in n ame n3 dmo0 n4 dmo1 n5 dmo2 n22 wr n23 rd n24 cs n25 rdy n26 addr7 p1 dgnd p2 dvdd p3 test p4 txon p5 dvdd p22 d0 p23 dgnd p24 pclk p25 dvdd p26 int r1 e3clk r2 dgnd r3 agnd r4 avdd r5 sfm_en r22 d7 r23 d6 r24 d5 r25 d4 r26 d1 t1 ds3clk t2 agnd t3 rxneg/lcv7 t4 rxclk7 t5 rxpos7 t22 rxpos5 p in p in n ame t23 rxclk5 t24 rxneg/lcv5 t25 avdd t26 d2 u1 sts-1clk/12m u2 agnd u3 rlos7 u4 rxneg/lcv9 u5 rlol9 u22 rlol3 u23 rxneg/lcv3 u24 rlos5 u25 agnd u26 d3 v1 dgnd v2 clkout7 v3 dvdd v4 rxclk9 v5 dgnd v22 dgnd v23 rxclk3 v24 dvdd v25 clkout5 v26 dgnd w1 dvdd w2 rlol7 w3 clkout9 w4 txneg9 w5 clkout11 w22 clkout1 w23 txneg3 w24 clkout3 w25 rlol5 w26 dvdd p in p in n ame xrt75r12d 16 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer y1 txneg7 y2 dgnd y3 rxpos9 y4 txclk9 y5 dvdd y22 dvdd y23 txclk3 y24 rxpos3 y25 dgnd y26 txneg5 aa1 txpos7 aa2 txclk7 aa3 rlos9 aa4 txpos9 aa5 txclk11 aa22 txclk1 aa23 txpos3 aa24 rlos3 aa25 txclk5 aa26 txpos5 ab1 rlol11 ab2 txneg11 ab3 txpos11 ab4 tdi ab5 tck ab6 avdd ab7 agnd ab8 mtip9 ab9 avdd ab10 agnd ab11 mtip7 ab12 rvdd7 ab13 rgnd7 ab14 rgnd5 p in p in n ame ab15 rvdd5 ab16 mring5 ab17 agnd ab18 avdd ab19 mring3 ab20 agnd ab21 avdd ab22 agnd ab23 tms ab24 txpos1 ab25 txneg1 ab26 rlol1 ac1 rxneg/lcv11 ac2 rxclk11 ac3 dgnd ac4 mring11 ac5 rvdd11 ac6 dgnd ac7 dgnd ac8 mring9 ac9 rgnd9 ac10 mring7 ac11 dgnd ac12 dgnd ac13 rtip7 ac14 dgnd ac15 mtip5 ac16 dgnd ac17 agnd ac18 rvdd3 ac19 mtip3 ac20 dgnd ac21 agnd ac22 rvdd1 p in p in n ame ac23 mring1 ac24 dgnd ac25 rxclk1 ac26 rxneg/lcv1 ad1 rxpos11 ad2 rlos11 ad3 ttip11 ad4 mtip11 ad5 rring11 ad6 dvdd ad7 ttip9 ad8 agnd ad9 rring9 ad10 agnd ad11 ttip7 ad12 dvdd ad13 rring7 ad14 dvdd ad15 agnd ad16 ttip5 ad17 agnd ad18 rring3 ad19 agnd ad20 ttip3 ad21 agnd ad22 rring1 ad23 mtip1 ad24 tring1 ad25 rlos1 ad26 rxpos1 ae1 agnd ae2 tdo ae3 tring11 ae4 tvdd11 p in p in n ame ae5 rtip11 ae6 tgnd9 ae7 tring9 ae8 dgnd ae9 rtip9 ae10 tvdd7 ae11 tring7 ae12 agnd ae13 agnd ae14 rring5 ae15 tvdd5 ae16 tring5 ae17 dgnd ae18 rtip3 ae19 tvdd3 ae20 tring3 ae21 dgnd ae22 rtip1 ae23 tvdd1 ae24 ttip1 ae25 trst ae26 agnd af1 agnd af2 agnd af3 dvdd af4 tgnd11 af5 rgnd11 af6 tvdd9 af7 dvdd af8 dvdd af9 rvdd9 af10 tgnd7 af11 dvdd af12 avdd p in p in n ame xrt75r12d 17 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 af13 avdd af14 rtip5 af15 tgnd5 af16 dvdd af17 dvdd af18 rgnd3 af19 tgnd3 af20 dvdd af21 dvdd af22 rgnd1 af23 tgnd1 af24 dvdd af25 agnd af26 agnd p in p in n ame xrt75r12d 18 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer functional description the xrt75r12d is a twelve chann el fully integrated line inte rface unit feat uring exar?s r 3 technology (reconfigurable, relayless redundancy) for e3/ds3/s ts-1 applications. the liu incorporates 12 independent receivers, transmitters and jitter attenua tors in a single 420 lead tbga package. each channel can be independently programmed to support e3, ds-3 or sts-1 line rates using one input clock reference of 12.288mhz in single frequency mode (sfm ). the liu is responsible for providing the physical connection between a line interface and an aggregate ma pper or framing device. along with the analog-to- digital processing, the liu offers monitoring and diagnostic features to help optimize network design implementation. a key char acteristic within the network topology is automa tic protection switching (aps). exar?s proven expertise in providing redundany solu tions has paved the way for r 3 technology. 1.0 r 3 technology (reconfigurable, relayless redundancy) redundancy is used to introduce re liability and protection into network card design. the redundant card in many cases is an exact replicate of the primary card, such that when a failure occurs the network processor can automatically switch to the backup ca rd. exar?s r 3 technology has re-defined e3/ds-3/sts-1 liu design for 1:1 and 1+1 redund ancy applications. without re lays and one bill of material s, exar offers multi-port, integrated liu solutions to assist high density aggr egate applications and framin g requirements with reliability. the following section can be used as a reference for implementing r 3 technology with exar?s world leading line interface units. 1.1 network architecture a common network design that supports 1:1 or 1+1 redundancy consists of n primary cards along with n backup cards that connect into a mid-plane or back-pl ane architecture without transformers installed on the network cards. in addition to the network cards, the design has a line interface card with one source of transformers, connectors, and protection components t hat are common to both network cards. with this design, the bill of materials is reduced to the fewest amount of components. see figure 2 . for a simplified block diagram of a typical redundancy design. f igure 2. n etwork r edundancy a rchitecture line interface card primary line card framer/ mapper liu back plane or mid plane tx rx 31.6 ? 31.6 ? 0.01 f 0.01 f 1:1 1:1 redundant line card framer/ mapper liu tx rx 31.6 ? 31.6 ? 0.01 f 0.01 f 37.5? 37.5? gnd xrt75r12d 19 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 2.0 clock synthesizer the liu uses a flexible user interfac e for accepting clock references to generate the internal master clocks used to drive the liu. the reference clock used to supply the microprocessor timing is generated from the ds- 3 or sfm clock input. therefore, if the chip is config ured for sts-1 only or e3 only, then the ds-3 input pin must be connected to the sts-1 pin or e3 pin respectively. in ds-3 mode or when sfm is used, the sts-1 and e3 input pins can be left unconnected. if sfm is enabled by pu lling the sfm_en pin "high", 12.288mhz is the only clock reference necessary to generate ds-3, e3, or sts-1 line rates and the microprocessor timing. a simplified block diagram of the clock synthesizer is shown in figure 3 . reference clock performance specifications can be found on table 2 below. n otes : 1. required to meet bellcore gr-499 specification on fr equency stability requirements. however, the liu can functionally operate with 100 ppm without meeting the required specifications. 2. reference clock jitter limits are required for the transmit output to meet itu-t and bellcore system level jitter requirements. f igure 3. s implified b lock d iagram of the i nput c lock c ircuitry d riving the m icroprocessor t able 2: r eference c lock p erformance s pecifications s ymbol p arameter m in t yp m ax u nits ref duty reference clock duty cycle 40 60 % ref e3 e3 reference clock frequency tolerance 1 -20 +20 ppm ref ds3 ds3 reference clock frequency tolerance 1 -20 +20 ppm ref sts1 sts-1 reference clock frequency tolerance 1 -20 +20 ppm ref sfm sfm reference clock frequency tolerance 1 -20 +20 ppm t rise_refclk reference clock rise time (10% to 90%) 5 ns t fall_refclk reference clock fall time (90% to 10%) 5 ns clk jit reference clock jitter stability 2 0.005 ui p2p clock synthesizer processor lol_n ds3clk sfm_en sts-1clk/12m e3clk clkout_n 0 1 xrt75r12d 20 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 2.1 clock distribution network cards that are designed to support multiple line rates which are not configured for single frequency mode should ensure that a clock is applied to the ds3clk input pin. for example: if the network card being supplied to an isp requires e3 only, the ds-3 input clock reference is still necessary to provide read and write access to the internal microprocessor. therefore, the e3 mode requires two input clock references. if however, multiple line rate s will not be supported, i.e. e3 only, then the ds3clk input pi n may be hard wire connected to the e3clk input pin. n ote : for one input clock reference, the single frequency mode should be used. f igure 4. c lock d istribution c ongifured in e3 m ode w ithout u sing sfm clock synthesizer processor lol_n ds3clk e3clk clkout_n xrt75r12d 21 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 3.0 the receiver section the receiver is designed so that the liu can recover cl ock and data from an attenuated line signal caused by cable loss or flat loss acco rding to industry specificat ions. once data is recovered, it is processed and presented at the receiver outputs according to the form at chosen to interface with a framer/mapper or asic. this section describes the detailed operation of various blocks within the receive path. a simplified block diagram of the receive path is shown in figure 5 . 3.1 receive line interface physical layer devices are ac coupled to a line interfac e through a 1:1 transformer. the transformer provides isolation and a level shift by blocking the dc offset of the incoming data stream. the typical medium for the line interface is a 75 ? coxial cable. whether using e3, ds-3 or sts-1, the liu requires the same bill of materials, see figure 6 . 3.2 adaptive gain control (agc) the adaptive gain control circuit am plifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate . the agc has a dynamic range of 30 db. the peak detector provides feedback to the equalizer before slicing occurs. f igure 5. r eceive p ath b lock d iagram f igure 6. r eceive l ine i nterface c onnection channel n hdb3/ b3zs decoder mux agc/ equalizer peak detector los detector slicer jitter attenuator clock & data recovery rxclk_n rxpos_n rxneg/lcv_n rlos_n rtip_n rring_n ds-3/e3/sts-1 1:1 receiver 75 ? rlos_n rtip_n rring_n 37.5 ? 0.01 f 37.5 ? xrt75r12d 22 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 3.3 receive equalizer the equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for e3). th e equalizer also boosts the high frequency content of the signal to reduce inter-symbol interferen ce (isi) so that the slicer slices th e signal at 50% of peak voltage to generate positive and negative data. the equalizer c an be disabled by programming the appropriate register. 3.3.1 recommendations for equalizer settings the equalizer has two gain settings to provide optimu m equalization. in the case of normally shaped ds3/ sts-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the equalizer can be enabled. however, for square-sha ped pulses such as e3 or for ds3/sts-1 high pulses (that does not meet the pulse template requirements), it is recommended that the equalizer be disabled for cable length less than 300 feet. this would help to pr event over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characte ristics. the equalizer also contains an additional 20 db gain stage to provide the line moni toring capability (receive monitor mode) of the resistively attenuated signals which may have 20db flat loss. the equaliz er and the equalizer gain mode can be enabled by programming the appropriate register. however, enablin g the equalizer gain mode (receive monitor mode) suppresses the internal lo s circuitry and los will never assert nor los be declared when operating with receive monitor mode enabled. n ote : the results of extensive testing indicate that even when the equalizer was enabled, regardless of the cable length, the integrity of the e3 signal was restored properly ov er 0 to 12 db cable loss at industrial temperature. 3.4 clock and data recovery the clock and data recovery circuit extracts the embedded clock, rxclk_n from the sliced digital data stream and provides the retimed data to the b3zs (hdb3) decoder. the clock recovery pll can be in one of the following two modes: 3.4.1 data/clock recovery mode in the presence of input line signals on the rtip_n an d rring_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the rxclk_n out pins is the recovered clock signal. 3.4.2 training mode in the absence of input signals at rtip_n and rring_n pins, or when t he frequency difference between the recovered line clock signal and the reference clock appli ed on the exclk_n input pins exceed 0.5%, a loss of lock condition is declared by toggling rlol_n output pi n ?high? or setting the rlol_n bit to ?1? in the control register. also, the clock output on the rxclk_n pins are the same as the reference channel clock. f igure 7. acg/e qualizer b lock d iagram agc/ equalizer peak detector los detector slicer rtip_n rring_n xrt75r12d 23 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 3.5 los (loss of signal) detector 3.5.1 ds3/sts-1 los condition a digital loss of signal (dlos) condition occurs when a string of 175 75 consecutive zeros occur on the line. when the dlos condition occu rs, the dlos_n bit is set to ?1? in the status control register. dlos condition is cleared when the detected average pulse density is grea ter than 33% for 175 75 pulses. analog loss of signal (alos) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the table 3 .the status of the alos condition is reflected in the alos_n status control register. rlos is the logical or of the dlos and alos states. when the rlos condition occurs the rlos_n output pin is toggled ?high? and the rlos_n bit is set to ?1? in the status control register. 3.5.2 disabling alos/dlos detection for debugging purposes it is useful to disable the alos and/or dlos detection. writing a ?1? to both alosdis_n and dlosdis_n bits disables t he los detection on a per channel basis. 3.5.3 e3 los condition: if the level of incoming line signal drops below the threshold as described in the itu-t g.775 standard, the los condition is detected. loss of signal is defined as no transitions for 10 to 255 consecutive zeros. no transitions is defined as a signal level between 15 and 35 db below the normal. this is illustrated in figure 8 . the los condition is cleared within 10 to 255 ui after restoration of the incoming line signal. figure 9 shows the los declaration and clearance conditions. t able 3: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of reqen (ds3 and sts-1 a pplications ) a pplication reqen s etting s ignal l evel to d eclare alos d efect s ignal l evel to c lear alos d efect ds3 0 < 41mvpk > 102mvpk 1 < 52mvpk > 117mvpk sts-1 0 < 51mvpk > 114mvpk 1 < 58mvpk > 133mvpk f igure 8. l oss o f s ignal d efinition for e3 as per itu-t g.775 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared xrt75r12d 24 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 3.5.4 interference tolerance for e3 mode, itu-t g.703 recommendation specifies that th e receiver be able to recover error free clock and data in the presence of a sinusoidal interferi ng tone signal. for ds3 and sts-1 modes, the same recommendation is being used. figure 10 shows the configuration to test the interference margin for ds3/ sts1. figure 11 shows the set up for e3. f igure 9. l oss of s ignal d efinition for e3 as per itu-t g.775. f igure 10. i nterference m argin t est s et up for ds3/sts-1 f igure 11. i nterference m argin t est s et up for e3. actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 compliance g.775 compliance 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rtip/ rring rlos output pin sine wave generator pattern generator 2 23 -1 prbs n s attenuator test equipment dut xrt75r12d ds3 = 22.368 mhz sts-1 = 25.92 mhz cable simulator attenuator 1 n s sine wave generator 17.184mhz signal source 2 23 -1 prbs attenuator 2 test equipment dut xrt75r12d cable simulator xrt75r12d 25 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 4: i nterference m argin t est r esults m ode c able l ength (a ttenuation ) i nterference t olerance e3 0 db equalizer ?in? -17 db 12 db -14 db ds3 0 feet -15 db 225 feet -15 db 450 feet -14 db sts-1 0 feet -15 db 225 feet -14 db 450 feet -14 db xrt75r12d 26 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 3.5.5 muting the recovered data with los condition: when the los condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the rx clk_n output pin. the data on the rxpos_n and rxneg_n pins can be forced to zero by setting the losmut_n bi ts in the individual channel control register to ?1?. n ote : when the los condition is cleared, the recovere d data is output on rxpos_n and rxneg_n pins. 3.6 b3zs/hdb3 decoder the decoder block takes the output from the clock and da ta recovery block and decodes the b3zs (for ds3 or sts-1) or hdb3 (for e3) encoded line signal and detect s any coding errors or excessive zeros in the data stream. whenever the input signal violates the b3zs or hdb3 coding sequence for bipolar violation or contains three (for b3zs) or four (for hdb3) or more co nsecutive zeros, an active ? high? pulse is generated on the rlcv_n output pins to indicate line code violation. f igure 12. r eceiver d ata output and code violation timing symbol parameter min typ max units rxclk duty cycle 45 50 55 % rxclk frequency e3 ds-3 sts-1 34.368 44.736 51.84 mhz mhz mhz t rrx rxclk rise time (10% o 90%) 2 4 ns t frx rxclk falling time (10% to 90%) 2 4 ns t co rxclk to rpos/rneg delay time 4 ns t lcvo rxclk to rising edge of lcv output delay 2.5 ns rxclk t rrx t frx rpos or rneg lcv t lcvo t co xrt75r12d 27 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 4.0 the transmitter section the transmitter is designed so that the liu can acce pt serial data from a local device, encode the data properly, and then output an analog pulse according to the pulse shape chosen in the appropriate registers. this section describes the detailed operation of variou s blocks within the transmit path. a simplified block diagram of the transmit path is shown in figure 13 . transmit digital input interface the method for applying data to the transmit inputs of the liu is a serial interfac e consisting of txclk, txpos, and txneg. for single rail mode, only txclk and txpos are necessary for providing the local data from a framer device or asic. data can be sampled on eith er edge of the input clock signal by programming the appropriate register. a typical interface is shown in figure 14 . f igure 13. t ransmit p ath b lock d iagram f igure 14. t ypical interface between terminal equipment and the xrt75r12d ( dual - rail data ) channel n device monitor mtip_n mring_n dmo_n timing control tx pulse shaping hdb3/ b3zs encoder tx control jitter attenuator mux line driver txon txclk_n txpos_n txneg_n ttip_n tring_n terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu transmit logic block txpos txneg txlineclk tpdata tndata txclk xrt75r12d 28 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer f igure 15. t ransmitter t erminal i nput t iming symbol parameter min typ max units txclk duty cycle 30 50 70 % txclk frequency e3 ds-3 sts-1 34.368 44.736 51.84 mhz mhz mhz t rtx txclk rise time (10% to 90%) 4 ns t ftx txclk fall time (10% to 90%) 4 ns t tsu tpdata/tndata to txclk falling set up time 3 ns t tho tpdata/tndata to txclk falling hold time 3 ns f igure 16. s ingle -r ail or nrz d ata f ormat (e ncoder and d ecoder are e nabled ) tpdata or tndata ttip or tring txclk t tsu t tho t rtx t ftx txclk tpdata data 1 1 0 xrt75r12d 29 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 4.1 transmit clock the transmit clock applied via txclk_n pins, for the se lected data rate (for e3 = 34.368 mhz, ds3 = 44.736 mhz or sts-1 = 51.84 mhz), is duty cycle corrected by the internal pll circuit to provide a 50% duty cycle clock to the pulse shaping circuit. this allows a 30% to 70% duty cycle transmit clock to be supplied. 4.2 b3zs/hdb3 e ncoder when the single-rail (nrz) data format is selected, the encoder block encodes the data into either b3zs format (for either ds3 or sts- 1) or hdb3 format (for e3). 4.2.1 b3zs encoding an example of b3zs encoding is shown in figure 18 . if the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either b0v or 00v, where ?b? refers to bipolar pulse that is compliant with the alternating polarity requirement of the ami (alternate mark inversion) line code and ?v? refers to a bipolar violation (e.g., a bipolar pulse th at violates the ami line code). the substitution of b0v or 00v is made so that an odd number of bipolar pulses exist between any two consec utive violation (v) pulses. this avoids the introduction of a dc component into the line signal. 4.2.2 hdb3 encoding an example of the hdb3 encoding is shown in figure 19 . if the hdb3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000v or b00v pattern. the substitution code is made in such a way that an odd number of pulses exist betwee n any consecutive v pulses. this avoids the introduction of dc component into the analog signal. f igure 17. d ual -r ail d ata f ormat ( encoder and decoder are disabled ) f igure 18. b3zs e ncoding f ormat txclk tpdata tndata data 1 1 0 000 1 1 1 1 1 1 1 v b v 1 0 00 00 0 0 0 0 0 0 0 000 v bv 0 00 tclk line signal tpdata xrt75r12d 30 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 4.3 t ransmit p ulse s haper the transmit pulse shaper converts the b3zs encoded digital pulses into a single analog alternate mark inversion (ami) pulse that meets the industry standard mask template requirements for sts-1 and ds3. for e3 mode, the pulse shaper converts the hdb3 encoded pulses into a single full amplitude square shaped pulse with very little slope. the pulse shaper block also includes a tr ansmit build out circuit, which can either be disabled or enabled by setting the txlev_n bit to ?1? or ?0? in the control register. for ds3/sts-1 rates, the transmit build out circuit is used to shape the transmit wavefo rm that ensures that transmit pulse template requirements are met at the cross-connect syst em. the distance between the transmitter output and the cross-connect system can be between 0 to 450 feet . for e3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no cr oss-connect system pulse template requirements, the transmit build out cir cuit is always disabled. the diff erential line driver increases the transmit waveform to appropriate level and drives into the 75 ? load as shown in figure 20 . 4.3.1 guidelines for using tr ansmit build out circuit if the distance between the transmitter and the dsx3 or stsx-1, cross-connect system, is less than 225 feet, enable the transmit build out circuit by setting the txl ev_n control bit to ?0?. if the distance between the transmitter and the dsx3 or stsx-1 is greater than 225 feet, disable the transmit build out circuit. f igure 19. hdb3 e ncoding f ormat f igure 20. t ransmit p ulse s hape t est c ircuit 0 0 000 1 1 1 1 1 1 1 v b v 1 00 00 0 0 0 0 0 0 0 0 00 v 0 00 tclk line signal tpdata ttip(n) tring(n) 1:1 r3 75 ? txpos(n) txneg(n) txlineclk(n) tpdata(n) tndata(n) txclk(n) 31.6 ? + 1% 31.6 ? +1% r1 r2 xrt75r12d 31 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 4.4 e3 line side parameters the xrt75r12d line output at the transformer output meets the pulse shape specified in itu-t g.703 for 34.368 mbits/s operation. the pulse mask as specif ied in itu-t g.703 for 34.368 mbits/s is shown in figure 21 . f igure 21. p ulse m ask for e3 (34.368 mbits / s ) interface as per itu - t g. 7 0 3 t able 5: e3 t ransmitter line side output and receiver line side input specifications parameter min typ max units t ransmitter line side output characteristics transmit output pulse amplitude (measured at secondar y of the transformer) 0.90 1.00 1.10 v pk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns transmit intr insic jitter 0.02 0.05 ui pp r eceiver line side input characteristics receiver sensitivit y (length of cable) 900 1200 feet interference margin -20 -14 db jitter tolerance @ jitter frequency 800khz 0.15 0.28 ui pp signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db 0% 50% v = 100% 14.55ns nom inal pulse 12.1ns (14.55 - 2.45) 17 ns (14.55 + 2.45) 8.65 ns 10% 10% 20% xrt75r12d 32 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer n ote : the above values are at ta = 25 0 c and v dd = 3.3 v 5%. occurence of los to los declaration time 10 255 ui termination of los to los clearance time 10 255 ui f igure 22. b ellcore gr-253 core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications t able 6: sts-1 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude lower curve -0.85 < t < -0.38 - 0.03 -0.38 < t < 0.36 0.36 < t < 1.4 - 0.03 upper curve -0.85 < t < -0.68 0.03 t able 5: e3 t ransmitter line side output and receiver line side input specifications parameter min typ max units sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 - 0.8 - 0.7 - 0. 6 - 0. 5 -0.4 -0.3 - 0.2 - 0.1 0 0 . 1 0 .2 0 .3 0 . 4 0.5 0 .6 0 . 7 0 . 8 0 .9 1 1 . 1 1 .2 1 . 3 1 . 4 time, in ui normalized amplitude lower curve upper curve 0.5 1 2 -- -1 t 0.18 ----------- + ? ? ? ? ?? ?? ?? sin + 0.03 ? xrt75r12d 33 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 n ote : the above values are at ta = 25 0 c and v dd = 3.3 v 5%. -0.68 < t < 0.26 0.26 < t < 1.4 0.1 + 0.61 x e -2.4[t-0.26] t able 7: sts-1 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-253) p arameter m in t yp m ax u nits t ransmitter line side output characteristics transmit output pulse amplitude (measured with txlev = 0) 0.65 0.75 0.90 v pk transmit output pulse amplitude (measured with txlev = 1) 0.90 1.00 1.10 v pk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.90 1.00 1.10 transmit intr insic jitter 0.02 0.05 ui pp r eceiver line side input characteristics receiver sensitivit y (length of cable) 900 1100 feet jitter tolerance @ jitter frequency 400 khz 0.15 ui pp signal level to declare loss of signal refer to table 3 signal level to clear loss of signal refer to table 3 t able 6: sts-1 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude 0.5 1 2 -- -1 t 0.34 ----------- + ? ? ? ? ?? ?? ?? sin + 0.03 + xrt75r12d 34 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer f igure 23. t ransmit o uput p ulse t emplate for ds3 as per b ellcore gr-499 t able 8: ds3 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude lower curve -0.85 < t < -0.36 - 0.03 -0.36 < t < 0.36 0.36 < t < 1.4 - 0.03 upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.36 0.36 < t < 1.4 0.08 + 0.407 x e -1.84[t-0.36] ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0. 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1. 1 1.2 1. 3 1.4 time, in ui normalized amplitude lower curve upper curve 0.5 1 2 -- -1 t 0.18 ----------- + ? ? ? ? ?? ?? ?? sin + 0.03 ? 0.5 1 2 -- -1 t 0.34 ----------- + ? ? ? ? ?? ?? ?? sin + 0.03 + xrt75r12d 35 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 n ote : the above values are at ta = 25 0 c and v dd = 3.3v 5%. t able 9: ds3 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-499) p arameter m in t yp m ax u nits t ransmitter line side output characteristics transmit output pulse amplitude (measured with txlev = 0) 0.65 0.75 0.85 v pk transmit output pulse amplitude (measured with txlev = 1) 0.90 1.00 1.10 v pk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.90 1.00 1.10 transmit intr insic jitter 0.02 0.05 ui pp r eceiver line side input characteristics receiver sensitivit y (length of cable) 900 1100 feet jitter tolerance @ 400 khz (cat ii) 0.15 ui pp signal level to declare loss of signal refer to table 3 signal level to clear loss of signal refer to table 3 xrt75r12d 36 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 4.5 transmit drive monitor this feature is used for monitoring the transmit line for oc currence of fault conditions such as a short circuit on the line or a defective line driver. to activate this fu nction, connect mtip_n pins to the ttip_n lines via a 270 ? resistor and mring_n pins to tring_n lines via 270 ? resistor as shown in figure 24 . when the mtip_n and mring_n are connected to the ttip_n and tring_n lines, the drive monitor circuit monitors the line for transitions. t he dmo_n (drive monitor output) will be asserted ?low? as long as the transitions on the line are detected via mtip_n and mrin g_n. if no transitions on the line are detected for 128 32 txclk_n periods, the dmo_n output toggles ?high? and when the transitions are detected again, dmo_n toggles ?low?. n ote : the drive monitor circuit is only for diagnostic purpose and does not have to be used to operate the transmitter. 4.6 transmitter section on/off the transmitter section of each channel can either be turned on or off. to turn on the transmitter, set the input pin txon to ?high? and write a ?1? to the txon_n control bit. when the tr ansmitter is turned off, ttip_n and tring_n are tri-stated. n otes : 1. this feature provides support for redundancy. 2. if the xrt75r12d is configured in host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writ ing a ?1? to the txon_n control bits transfers the control to txon pin. f igure 24. t ransmit d river m onitor set - up . ttip(n) tring(n) 1:1 r3 75 ? txpos(n) txneg(n) txlineclk(n) tpdata(n) tndata(n) txclk(n) 31.6 ? + 1% 31.6 ? +1% r1 r2 mtip(n) mring(n) 270 ? 270 ? r1 r2 xrt75r12d 37 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 5.0 jitter there are three fundamental parameters that describe circuit performance relative to jitter ? jitter tolerance ? jitter transfer ? jitter generation 5.1 j itter t olerance jitter tolerance is a measure of how well a clock and data recovery unit can successf ully recover data in the presence of various forms of jitter. it is characterized by the amount of jitter required to produce a specified bit error rate. the tolerance depends on the frequency content of the jitter. jitter tolerance is measured as the jitter amplitude over a jitter spectrum for which the clo ck and data recovery unit achieves a specified bit error rate (ber). to measure the jitter tolerance as shown in figure 25 , jitter is introduced by the sinusoidal modulation of the serial data bit sequence. input jitter tolerance requirements are specified in terms of compliance with jitter ma sk which is represented as a combination of points. each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency. 5.1.1 ds3/sts-1 jitter tolerance requirements bellcore gr-499 core spec ifies the minimum requirement of jitter tolerance for category i and category ii. the jitter tolerance requirement for category ii is the most stringent. figure 26 shows the jitter tolerance curve as per gr-499 specification. f igure 25. j itter t olerance m easurements freq synthesizer pattern generator dut xrt75r12d error detector modulation freq. data clock xrt75r12d 38 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 5.1.2 e3 jitter tolerance requirements itu-t g.823 standard specifies that the clock and data recove ry unit must be able to to lerate jitter up to certain specified limits. figure 27 shows the tolerance curve. as shown in the figures above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the e3/ds3/sts-1 co mpliant component must tolerate. table 10 below shows the jitter amplitude versus the modulation frequency for various standards. f igure 26. i nput j itter t olerance f or ds3/sts-1 f igure 27. i nput j itter t olerance for e3 0.01 0.03 15 1.5 0.3 2 20 0.15 jitter amplitude (ui pp ) jitter frequency (khz) 10 5 0.3 100 0.1 gr-253 sts-1 gr-499 cat ii gr-499 cat i 64 41 xrt75r12d 0.1 1.5 1 10 jitter amplitude (ui pp ) jitter frequency (khz) 800 itu-t g.823 64 10 0.3 xrt75r12d xrt75r12d 39 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 5.2 j itter t ransfer jitter transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. there are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the highest ratio above 0db and jitter tr ansfer bandwidth. the overall jitter transfer bandwidth is controlled by a low bandwidth loop, typically using a volt age-controlled crystal oscillator (vcxo). the jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in db. a negative db jitter transfer indicates the element removed jitter. a positive db jitter transfer indicates the element added jitter. a zero db jitter tr ansfer indicates the element had no effect on jitter. table 11 shows the jitter transfer characteristics and/or jitte r attenuation specifications for various data rates: n ote : the above specifications can be met only with a jitte r attenuator that supports e3/ds3/sts-1 rates. 5.3 jitter attenuator an advanced crystal-less jitter attenuator per channel is included in the xrt75r12d. the jitter attenuator requires no external crystal nor high-frequency reference clock. by clearing or setting the jatx/rx_n bits in the channel control registers selects the jitter attenuator either in the receive or transmit path on per channel basis. the fifo size can be either 16-bit or 32-bit . the bits ja0_n and ja1_n can be set to appropriate combination to select the different fifo sizes or to disable the jitter attenuator on a per channel basis. data is clocked into the fifo with the asso ciated clock signal (txclk or rxclk) and clocked out of the fifo with the dejittered clock. when the fifo is within two bits of over flowing or underflowing, the fifo limit status bit, fl_n is set to ?1? in the alarm status register. reading this bit clears the fifo and resets the bit into default state. n ote : it is recommended to select the 16-bit fifo for delay-sensitive applications as well as for removing smaller amounts of jitter. table 12 specifies the jitter tr ansfer mask requirements for various data rates: t able 10: j itter a mplitude versus m odulation f requency (j itter t olerance ) b it r ate ( kb / s ) s tandard i nput j itter a mplitude (ui p - p ) m odulation f requency a1 a2 a3 f 1(h z ) f 2(h z ) f 3( k h z ) f 4( k h z ) f 5( k h z ) 34368 itu-t g.823 1.5 0.15 - 100 1000 10 800 - 44736 gr-499 core cat i 5 0.1 - 10 2.3k 60 300 - 44736 gr-499 core cat ii 10 0.3 - 10 669 22.3 300 - 51840 gr-253 core cat ii 15 1.5 0.15 10 30 300 2 20 t able 11: j itter t ransfer s pecification /r eferences e3 ds3 sts-1 etsi tbr-24 gr-499 core section 7.3.2 category i and category ii gr-253 core section 5.6.2.1 xrt75r12d 40 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer the jitter attenuator within the xrt75r12d meets the la test jitter attenuation spec ifications and/or jitter transfer characteristics as shown in the figure 28 . 5.3.1 j itter g eneration jitter generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. jitter generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. the bandwidth is set according to the data rate. in general, the jitter is measured over a band of frequencies. t able 12: j itter t ransfer p ass m asks r ate ( kbits ) m ask f1 (h z ) f2 (h z ) f3 (h z ) f4 ( k h z ) a1( db) a2( db) 34368 g. 8 2 3 etsi-tbr-24 100 300 3 k 800 k 0.5 -19.5 44736 gr-499, cat i gr-499, cat ii gr-253 core 10 10 10 10k 56.6k 40 - - - 15k 300k 15k 0.1 0.1 0.1 - - - 51840 gr-253 core 10 40k - 400k 0.1 - f igure 28. j itter t ransfer r equirements and j itter a ttenuator p erformance f1 a1 f2 jitter amplitude jitter frequency (khz) a2 f3 f4 xrt75r12d 41 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 6.0 diagnostic features 6.1 prbs generator and detector the xrt75r12d contains an on-chip pseudo random bina ry sequence (prbs) generator and detector for diagnostic purpose . with the prbsen_n bit = ?1?, th e transmitter will send out prbs of 2 23 -1 in e3 rate or 2 15 -1 in sts-1/ds3 rate. at the same time, the receiver prbs detector is also enabled. when the correct prbs pattern is detected by the rece iver, the rneg/lcv pin will go ?low? to indicate prbs synchronization has been achieved. when the prbs de tector is not in sync the prbsls bi t will be set to ?1? and rneg/lcv pin will go ?high?. with the prbs mode enabled, the user can also insert a single bit error by togg ling ?insprbs? bit. this is done by writing a ?1? to insprbs bi t. the receiver at rneg/lcv pin will pulse ?high? for one rxclk cycle for every bit error detected. any subsequent single bit erro r insertion must be done by first writing a ?0? to insprbs bit and followed by a ?1?. figure 29 shows the status of rneg/lcv pin when th e xrt75r12d is configured in prbs mode. n ote : in prbs mode, the device is forced to operate in single-rail mode. f igure 29. prbs mode rxclk rxneg/lcv sync loss prbs sync single bit error xrt75r12d 42 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 6.2 loopbacks the xrt75r12d offers three loopback modes for diagnostic purposes. the loopback modes are selected via the rlb_n and llb_n bits n the channel control registers select the loopback modes. 6.2.1 analog loopback in this mode, the transmitter outputs ttip_n and tring_n are internally connected to the receiver inputs rtip_n and rring_n as shown in figure 30 . data and clock are output at rxclk_n, rxpos_n and rxneg_n pins for the corresponding transceiver. analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path. n otes : 1. in the analog loopback mode, data is also output via ttip_n and tring_n pins. 2. signals on the rtip_n and rring_n pins are ignored during analog loopback. f igure 30. a nalog l oopback tring ttip rring rtip rxpos rxneg rxclk txneg txclk txpos hdb3/b3zs encoder hdb3/b3zs decoder jitter attenuator jitter attenuator timing control data & clock recovery tx rx xrt75r12d 43 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 6.2.2 digital loopback when the digital loopback is selected, the transmit clock txclk_n and transmit data inputs (txpos_n & txneg_n are looped back and output onto the rxclk_n, rxpos_n and rxneg_n pins as shown in figure 31 . 6.2.3 remote loopback with remote loopback activated as shown in figure 32 , the receive data on rtip and rring is looped back after the jitter attenuator (if selected in receive or transm it path) to the transmit pa th using rxclk as transmit timing. the receive data is also output via the rxpos and rxneg pins. n ote : input signals on txclk, txpos and txneg are ignored during remote loopback. f igure 31. d igital l oopback f igure 32. r emote l oopback tring ttip rring rtip rxpos rxneg rxclk txneg txclk txpos hdb3/b3zs encoder hdb3/b3zs decoder jitter attenuator jitter attenuator timing control data & clock recovery tx rx tring ttip rring rtip rxpos rxneg rxclk txneg txclk txpos hdb3/b3zs encoder hdb3/b3zs decoder jitter attenuator jitter attenuator timing control data & clock recovery tx rx xrt75r12d 44 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 6.3 transmit all ones (taos) transmit all ones (taos) can be set by setting the taos _n control bits to ?1? in the channel control registers. when the taos is set, the transmit section generates and transmits a continuous ami all ?1?s? pattern on ttip_n and tring_n pins. the frequency of this ones patte rn is determined by txclk_ n. the taos data path is shown in figure 33 . taos does not operate in analog loopback or remote loopback modes, however will function in digital loopback mode. f igure 33. t ransmit a ll o nes (taos) tring ttip rring rtip rxpos rxneg rxclk txneg txclk txpos hdb3/b3zs encoder hdb3/b3zs decoder jitter attenuator jitter attenuator timing control data & clock recovery tx rx taos transmit all 1's xrt75r12d 45 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 7.0 microprocessor interface block the microprocessor interface section supports communi cation between the local microprocessor (p) and the liu. the xrt75r12d supports a parallel interface asynchronously or synchronously timed to the liu. the microprocessor interface is selected by the state of t he pmode input pin. selecting the microprocessor inter - face mode is shown in table 13 . the local p configures the liu by wr iting data into specific addressable, on-chip read/write registers. the p provides the signals which are required for a general purpose microprocessor to read or write data into these registers. the p also supports polled and interr upt driven environments. a simplified block diagram of the microprocessor is shown in figure 34 . t able 13: s electing the m icroprocessor i nterface m ode p mode m icroprocessor m ode "low" asynchronous mode "high" synchronous mode f igure 34. s implified b lock d iagram of the m icroprocessor i nterface b lock microprocessor interface wr rd pmode rdy reset pclk cs int addr[7:0] d[7:0] xrt75r12d 46 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 7.1 t he m icroprocessor i nterface b lock s ignals the liu may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. these interface signals are de - scribed below in table 14 . the microprocessor interface can be config ured to operate in asynchronous mode or synchronous mode. t able 14: xrt75r12d m icroprocessor i nterface s ignals p in n ame t ype d escription pmode i microprocessor interface mode select input pin this pin is used to specify the microprocessor interface mode. d[7:0] i/o bi-directional data bus for register "read" or "write" operations. addr[7:0] i eight-bit address bus inputs the xrt75r12d liu microprocessor interface uses a direct address bus. this address bus is provided to permit the user to select an on-chip register for read/write access. cs i chip select input this active low signal sele cts the microprocessor interfac e of the xrt75r12d liu and enables read/write operations with the on-chip register locations. rd i read signal this active low input functions as the read signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a read operation has been requested and begins the proces s of the read cycle. wr i write signal this active low input functions as the write signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a write operation has been requested and begins the process of the write cycle. rdy o ready output this active low signal is provided by the liu device. it indicates that the cur - rent read or write cycle is complete, and the liu is waiting for the next command. int o interrupt output this active low signal is provided by the liu to alert the local mp that a change in alarm status has occured. this pin is reset upon read (rur) once the alarm sta - tus registers have been cleared. reset i reset input this active low input pin is used to reset the liu. xrt75r12d 47 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 7.2 a synchronous and s ynchronous d escription whether the liu is configured for asynchronous or synchronous mode, the following descriptions apply. the synchronous mode requires an input clock (pclk) to be used as the microprocessor timing reference. read and write operations are described below. read cycle (for pmode = "0" or "1") whenever the local p wishes to read the conten ts of a register, it should do the following. 1. place the address of the target register on the address bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables communication between the p and the liu microprocessor interface block. 3. next, the p should indicate that this current bus cycle is a read operation by toggling the rd input pin "low". this action enables the bi-directio nal data bus output drivers of the liu. 4. after the p toggles the read signal "low", the liu will toggle the rdy output pin "low". the liu does this to inform the p that the data is available to be read by the p, and that it is ready for the next command. 5. after the p detects the rdy signal and has read the data, it can terminate the read cycle by toggling the rd input pin "high". 6. the cs input pin must be pulled "high" before a new command can be issued. write cycle (for pmode = "0" or "1") whenever a local p wishes to write a byte or word of data into a register within the liu, it should do the follow - ing. 1. place the address of the target register on the address bus input pins addr[7:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables communication between the p and the liu microprocessor interface block. 3. the p should then place the byte or word that it intends to write into the target register, on the bi-direc - tional data bus d[7:0]. 4. next, the p should indicate th at this current bus cycle is a write operation by toggling the wr input pin "low". this action enables the bi-directional data bus input drivers of the liu. 5. after the p toggles the write signal "low", the liu will toggle the rdy output pin "low". the liu does this to inform the p that the data has been written into the internal register location, and that it is ready for the next command. 6. the cs input pin must be pulled "high" before a new command can be issued. f igure 35. a synchronous p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations cs addr[7:0] d[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address xrt75r12d 48 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 15: a synchronous t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 0 - ns t 2 rd assert to rdy assert - 65 ns na rd pulse width (t 2 ) 70 - ns t 3 cs falling edge to wr assert 0 - ns t 4 wr assert to rdy assert - 65 ns na wr pulse width (t 4 ) 70 - ns f igure 36. s ynchronous p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations cs addr[7:0] d[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address pclk xrt75r12d 49 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 n ote : 1. this timing parameter is based on the frequency of the synchronous clock (pclk). to determine the access time, use the following formula: (pclk period * 2) + 5ns t able 16: s ynchronous t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 0 - ns t 2 rd assert to rdy assert - 35 ns, see note 1 na rd pulse width (t 2 ) 40 - ns t 3 cs falling edge to wr assert 0 - ns t 4 wr assert to rdy assert - 35 ns, see note 1 na wr pulse width (t 4 ) 40 - ns pclk period 15 ns pclk duty cycle pclk "high/low" time xrt75r12d 50 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 7.3 register map t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame 0x00 cr0 apst r/w aps transmit redundancy control register 0-5 c hannel 0 c ontrol r egisters 0x01 cr1 ier0 r/w source level interrupt enable register - ch 0 0x02 cr2 isr0 rur source level interrupt status register ch 0 0x03 cr3 as0 r/o alarm status register - ch 0 0x04 cr4 tc0 r/w transmit control register - ch 0 0x05 cr5 rc0 r/w receive control register - ch 0 0x06 cr6 cc0 r/w channel control register - ch 0 0x07 cr7 ja0 r/w jitter attenuator control register - ch 0 0x08 cr8 apsr r/w aps receive redundancy control register 0-5 0x09 0x0a cr10 em0 r/w error counter ms byte ch 0 0x0b cr11 el0 r/w error counter ls byte 0x0c cr12 eh0 r/w error counter holding register 0x0d 0x0e 0x0f 0x10 c hannel 1 c ontrol r egisters 0x11 cr17 ier1 r/w source level interrupt enable register - ch 1 0x12 cr18 isr1 rur source level interrupt status register - ch 1 0x13 cr19 as1 r/o alarm status register - ch 1 0x14 cr20 tc0 r/w transmit control register - ch 1 0x15 cr21 rc1 r/w receive control register - ch 1 0x16 cr22 cc1 r/w channel control register - ch 1 0x17 cr23 ja1 r/w jitter attenuator control register - ch 1 0x18 0x19 0x1a cr26 em1 r/w error counter msbyte ch 1 0x1b cr27 el1 r/w error counter lsbyte 0x1c cr28 eh1 r/w error counter holding register xrt75r12d 51 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 0x1d 0x1e 0x1f 0x20 c hannel 2 c ontrol r egisters 0x21 cr33 ier2 r/w source level interrupt enable register - ch 2 0x22 cr34 isr2 rur source level interrupt status register - ch 2 0x23 cr35 as2 r/o alarm status register - ch 2 0x24 cr36 tc2 r/w transmit control register - ch 2 0x25 cr37 rc2 r/w receive control register - ch 2 0x26 cr38 cc2 r/w channel control register - ch 2 0x27 cr39 ja2 r/w jitter attenuator control register - ch 2 0x28 0x29 0x2a cr42 em2 r/w error counter msbyte ch 2 0x2b cr43 el2 r/w error counter lsbyte 0x2c cr44 eh2 r/w error counter holding register 0x2d 0x2e 0x2f 0x30 c hannel 3 c ontrol r egisters 0x31 cr49 ier3 r/w source level interrupt enable register - ch 3 0x32 cr50 isr3 rur source level interrupt status register - ch 3 0x33 cr51 as3 r/o alarm status register - ch 3 0x34 cr52 tc3 r/w transmit control register - ch 3 0x35 cr53 rc3 r/w receive control register - ch 3 0x36 cr54 cc3 r/w channel control register - ch 3 0x37 cr55 ja3 r/w jitter attenuator control register - ch 3 0x38 0x39 0x3a cr58 em3 r/w error counter msbyte ch 3 t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 52 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 0x3b cr59 el3 r/w error counter lsbyte 0x3c cr60 eh3 r/w error counter holding register 0x3d 0x3e 0x3f 0x40 c hannel 4 c ontrol r egisters 0x41 cr65 ier4 r/w source level interrupt enable register - ch 4 0x42 cr66 isr4 rur source level interrupt status register - ch 4 0x43 cr67 as4 r/o alarm status register - ch 4 0x44 cr68 tc4 r/w transmit control register - ch 4 0x45 cr69 rc4 r/w receive control register - ch 4 0x46 cr70 cc4 r/w channel control register - ch 4 0x47 cr71 ja4 r/w jitter attenuator control register - ch 4 0x48 0x49 0x4a cr74 em4 r/w error counter msbyte ch 4 0x4b cr75 el4 r/w error counter lsbyte 0x4c cr76 eh4 r/w error counter holding register 0x4d 0x4e 0x4f 0x50 c hannel 5 c ontrol r egisters 0x51 cr81 ier5 r/w source level interrupt enable register - ch 5 0x52 cr82 isr5 rur source level interrupt status register - ch 5 0x53 cr83 as5 r/o alarm status register - ch 5 0x54 cr84 tc5 r/w transmit control register - ch 5 0x55 cr85 rc5 r/w receive control register - ch 5 0x56 cr86 cc5 r/w channel control register - ch 5 0x57 cr87 ja5 r/w jitter attenuator control register - ch 5 0x58 t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 53 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 0x59 0x5a cr90 em5 r/w error counter msbyte ch 5 0x5b cr91 el5 r/w error counter lsbyte 0x5c cr92 eh5 r/w error counter holding register 0x5d 0x5e 0x5f 0x60 cr96 cie r/w channel 0-5 interrupt enable flags 0x61 cr97 cis r/o channel 0-5 interrupt status flags 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x65 0x69 0x6a 0x6b 0x6c 0x6d 0x6e cr110 pn r/o device part number register 0x6f cr111 vn r/o chip revision number register 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 54 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 0x78 0x75 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 cr128 apst r/w aps transmit redundancy control register 6-11 c hannel 6 c ontrol r egisters 0x81 cr129 ier6 r/w source level interrupt enable register - ch 6 0x82 cr130 isr6 rur source level interrupt status register - ch 6 0x83 cr131 as6 r/o alarm status register - ch 6 0x84 cr132 tc6 r/w transmit control register - ch 6 0x85 cr133 rc6 r/w receive control register - ch 6 0x86 cr134 cc6 r/w channel control register - ch 6 0x87 cr135 ja6 r/w jitter attenuator control register - ch 6 0x88 cr136 apsr r/w aps receive redundancy control register 6-11 0x89 0x8a cr138 em6 r/w error counter msbyte ch 6 0x8b cr139 el6 r/w error counter lsbyte 0x8c cr140 eh6 r/w error counter holding register 0x8d 0x8e 0x8f 0x90 c hannel 7 c ontrol r egisters 0x91 cr145 ier7 r/w source level interrupt enable register - ch 7 0x92 cr146 isr7 rur source level interrupt status register - ch 7 0x93 cr147 as7 r/o alarm status register - ch 7 0x94 cr148 tc7 r/w transmit control register - ch 7 t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 55 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 0x95 cr149 rc7 r/w receive control register - ch 7 0x96 cr150 cc7 r/w channel control register - ch 7 0x97 cr151 ja7 r/w jitter attenuator control register - ch 7 0x98 0x99 0x9a cr154 em7 r/w error counter msbyte ch 7 0x9b cr155 el7 r/w error counter lsbyte 0x9c cr156 eh7 r/w error counter holding register 0x9d 0x9e 0x9f 0xa0 c hannel 8 c ontrol r egisters 0xa1 cr161 ier8 r/w source level interrupt enable register - ch 8 0xa2 cr162 isr8 rur source level interrupt status register - ch 8 0xa3 cr163 as8 r/o alarm status register - ch 8 0xa4 cr164 tc8 r/w transmit control register - ch 8 0xa5 cr165 rc8 r/w receive control register - ch 8 0xa6 cr166 cc8 r/w channel control register - ch 8 0xa7 cr167 ja8 r/w jitter attenuator control register - ch 8 0xa8 0xa9 0xaa cr170 em8 r/w error counter msbyte ch 8 0xab cr171 el8 r/w error counter lsbyte 0xac cr172 eh8 r/w error counter holding register 0xad 0xae 0xaf 0xb0 c hannel 9 c ontrol r egisters 0xb1 cr177 ier9 r/w source level interrupt enable register - ch 9 0xb2 cr178 isr9 rur source level interrupt status register - ch 9 t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 56 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 0xb3 cr179 as9 r/o alarm status register - ch 9 0xb4 cr180 tc9 r/w transmit control register - ch 9 0xb5 cr181 rc9 r/w receive control register - ch 9 0xb6 cr182 cc9 r/w channel control register - ch 9 0xb7 cr183 ja9 r/w jitter attenuator control register - ch 9 0xb8 0xb9 0xba cr186 em9 r/w error counter msbyte ch 9 0xbb cr187 el9 r/w error counter lsbyte 0xbc cr188 eh9 r/w error counter holding register 0xbd 0xbe 0xbf 0xc0 c hannel 10 c ontrol r egisters 0xc1 cr193 ier10 r/w source level interrupt enable register - ch 10 0xc2 cr194 isr10 rur source level interrupt status register - ch 10 0xc3 cr195 as10 r/o alarm status register - ch 10 0xc4 cr196 tc10 r/w transmit control register - ch 10 0xc5 cr197 rc10 r/w receive control register - ch 10 0xc6 cr198 cc10 r/w channel control register - ch 10 0xc7 cr199 ja10 r/w jitter attenuator control register - ch 10 0xc8 0xc9 0xca cr202 em10 r/w error counter msbyte ch 10 0xcb cr203 el10 r/w error counter lsbyte 0xcc cr204 eh10 r/w error counter holding register 0xcd 0xce 0xcf 0xd0 c hannel 11 c ontrol r egisters t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 57 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 0xd1 cr209 ier11 r/w source level interrupt enable register - ch 11 0xd2 cr210 isr11 rur source level interrupt status register - ch 11 0xd3 cr211 as11 r/o alarm status register - ch 11 0xd4 cr212 tc11 r/w transmit control register - ch 11 0xd5 cr213 rc11 r/w receive control register - ch 11 0xd6 cr214 cc11 r/w channel control register - ch 11 0xd7 cr215 ja11 r/w jitter attenuator control register - ch 11 0xd8 0xd9 0xda cr218 em11 r/w error counter msbyte ch 11 0xdb cr219 el11 r/w error counter lsbyte 0xdc cr229 eh11 r/w error counter holding register 0xdd 0xde 0xdf 0xe0 cr224 cie r/w channel 6-11 interrupt enable flags 0xe1 cr225 cis r/o channel 6-11 interrupt status flags 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe5 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 58 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf5 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff t able 17: c ommand r egister a ddress m ap , within the xrt75r12d a ddress (h ex ) c ommand r egister (d ecimal ) l abel t ype r egister n ame xrt75r12d 59 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 the global/chip-level registers the register set, within the xrt75r12d contains ten gl obal or chip-level register s. these registers control operations in more than one channel or apply to th e complete chip. this se ction will present detailed information on the global registers. register description - global registers t able 18: l ist and a ddress l ocations of g lobal r egisters a ddress c ommand r egister l abel t ype r egister n ame 0x00 cr0 apst r/w aps transmit redundancy control register 0-5 0x08 cr8 apsr r/w aps receive redundancy control register 0-5 0x80 cr128 apst r/w aps transmit redundancy control register 6-11 0x88 cr136 apsr r/w aps receive redundancy control register 6-11 0x60 cr96 cie r/w channel 0-5 interrupt enable flags 0x61 cr97 cis r/o channel 0-5 interrupt status flags 0xe0 cr224 cie r/w channel 6-11 interrupt enable flags 0xe1 cr225 cis r/o channel 6-11 interrupt status flags 0x6e cr110 pn rom device part number register 0x6f cr111 vn rom chip revision/version number register t able 19: aps/r edundancy t ransmit c ontrol r egister - cr0 (a ddress l ocation = 0 x 00) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved reserved txon ch 5 txon ch 4 txon ch 3 txon ch 2 txon ch 1 txon ch 0 r/w r/w r/w r/w r/w r/w b it n umber n ame t ype d escription 7,6 reserved 5 4 3 2 1 0 txon ch 5 txon ch 4 txon ch 3 txon ch 2 txon ch 1 txon ch 0 r/w transmit section on - channel n this read/write bit-field is used to turn on or turn off the transmit driver associ - ated with channel n. if the user turn s on the transmit driver, then channel n will transmit ds3, e3 or sts-1 pulses on t he line via the ttip_n and tring_ n output pins. conversely, if the user turns off the tran smit driver, then the ttip_n and tring_n output pins will be tri-stated. 0 - shuts off the transmit driver associated with channel n and tri-states the ttip_n and tring_ n output pins. 1 - turns on the transmit driver associated with channel n. n ote : the master txon control pin(pin # p4) must be in a high state (logic 1) for this operation to turn on any channel. xrt75r12d 60 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 20: aps/r edundancy t ransmit c ontrol r egister - cr8 (a ddress l ocation = 0 x 08) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved reserved txon ch 11 txon ch 10 txon ch 9 txon ch 8 txon ch 7 txon ch 6 r/w r/w r/w r/w r/w r/w b it n umber n ame t ype d escription 7,6 reserved 5 4 3 2 1 0 txon ch 11 txon ch 10 txon ch 9 txon ch 8 txon ch 7 txon ch 6 r/w transmit section on - channel n this read/write bit-field is used to turn on or turn off the transmit driver associ - ated with channel n on a per channel basis. if the user turns on the transmit driver, then channel n will transmit ds3, e3 or sts-1 pulses on the line via the ttip_n and tring_ n output pins. conversely, if the user turns off the transmit driver (for channel n), the ttip_n and tring_n output pins will be tri-stated. 0 - shuts off the transmit driver associated with channel n and tri-states the ttip_n and tring_ n output pins. 1 - turns on the transmit driver associated with channel n. n ote : the master txon control (pin # p4) must be in a high state (logic 1) for this operation to turn on any channel. xrt75r12d 61 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 21: c hannel l evel i nterrupt e nable r egister - cr96 (a ddress l ocation = 0 x 60) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved reserved channel 5 interrupt enable channel 4 interrupt enable channel 3 interrupt enable channel 2 interrupt enable channel 1 interrupt enable channel 0 interrupt enable r/w r/w r/w r/w r/w r/w register - cr96 (address location = 0x60) b it n umber n ame t ype d escription 7,6 unused 5 4 3 2 1 0 channel 5 interrupt enable channel 4 interrupt enable channel 3 interrupt enable channel 2 interrupt enable channel 1 interrupt enable channel 0 interrupt enable r/w channel n interrupt enable bit: this read/write bit is used to: ? to enable channel n for interrupt generation at the channel level ? to disable all interrupts associated with channel n within the xrt75r12d this is a "master" enable bit for each channel. this bit allows control on a per channel basis to signal the host of selected error conditions. if a bit is cleared, no interrupts from that channel will be sent to the host via the int . if the bit is set (logic 1), any generated interrupt in channel n that has been enabled in the interrupt enable register (iern) for the channel will activate the int pin to the host. 0 - disables all channel n related interrupts. 1 - enables channel n-related interrupts. the user must enable individual channel n related interrupts at the source level, before they are can generate an interrupt. xrt75r12d 62 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 22: c hannel l evel i nterrupt e nable r egister - cr224 (a ddress l ocation = 0 x e0) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved reserved channel 11 interrupt enable channel 10 interrupt enable channel 9 interrupt enable channel 8 interrupt enable channel 7 interrupt enable channel 6 interrupt enable r/w r/w r/w r/w r/w r/w register - cr224 (add ress location = 0xe0) b it n umber n ame t ype d escription 7,6 reserved 5 4 3 2 1 0 channel 11 interrupt enable channel 10 interrupt enable channel 9 interrupt enable channel 8 interrupt enable channel 7 interrupt enable channel 6 interrupt enable r/w channel n interrupt enable bit: this read/write bit is used to: ? to enable channel n for interrupt generation at the channel level ? to disable all interrupts associated with channel n within the xrt75r12d this is a "master" enable bit for each channel. this bit allows control on a per channel basis to signal the host of selected error conditions. if a bit is cleared, no interrupts from that channel will be sent to the host via the int pin. if the bit is set (logic 1), any generated interrupt in channel n that has been enabled in the interrupt enable register (iern) for the channel will activate the int pin to the host. 0 - disables all channel n related interrupts. 1 - enables channel n-related interrupts. the user must enable individual channel n related interrupts at the source level, before they are can generate an interrupt. xrt75r12d 63 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 23: c hannel l evel i nterrupt s tatus r egister - cr97 (a ddress l ocation = 0 x 61) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved reserved channel 5 interrupt status channel 4 interrupt status channel 3 interrupt status channel 2 interrupt status channel 1 interrupt status channel 0 interrupt status r/o r/o r/o r/o r/o r/o register - cr97 (address location = 0x61) b it n umber n ame t ype d escription 7, 6 reserved 5 4 3 2 1 0 channel 5 interrupt status channel 4 interrupt status channel 3 interrupt status channel 2 interrupt status channel 1 interrupt status channel 0 interrupt status r/o channel n interrupt status bit: this read-only bit-field indicates whether the xrt75r12d has a pending channel n-related interrupt that is awaiting service. the first six channels are serviced through this location and the other six at address 0xe1. these two registers are used by the host to identify the source channel of an active interrupt. 0 - indicates that there is no channel n-related interrupt awaiting ser - vice. 1 - indicates that there is at least one channel n-related interrupt awaiting service. in this case, the user's interrupt service routine should be written such that the microprocessor will now proceed to read out the contents of the source level interrupt status register - channel n (address locations = 0xn2) to determine the exact source of the interrupt request. n ote : once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out th e contents of the source-level interrupt status register bit, t hat corresponds to the interrupt request channel. xrt75r12d 64 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 24: c hannel l evel i nterrupt s tatus r egister - cr225 (a ddress l ocation = 0 x e1) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved reserved channel 11 interrupt status channel 10 interrupt status channel 9 interrupt status channel 8 interrupt status channel 7 interrupt status channel 6 interrupt status r/o r/o r/o r/o r/o r/o register - cr225 (address location = 0xe1) b it n umber n ame t ype d escription 7, 6 reserved 5 4 3 2 1 0 channel 11 interrupt status channel 10 interrupt status channel 9 interrupt status channel 8 interrupt status channel 7 interrupt status channel 6 interrupt status r/o channel n interrupt status bit: this read-only bit-field indicates whether the xrt75r12d has a pending channel n-related interrupt that is awaiting service. the last six channels are serviced through this location and the other six at address 0x61. these two registers are used by the host to identify the source channel of an active interrupt. 0 - indicates that there is no channel n-related interrupt awaiting ser - vice. 1 - indicates that there is at least one channel n-related interrupt awaiting service. in this case, the user's interrupt service routine should be written such that the microprocessor will now proceed to read out the contents of the source level interrupt status register - channel n (address locations = 0xn2) to determine the exact source of the interrupt request. n ote : once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out th e contents of the source-level interrupt status register bit, that corresponds to the interrupt request channel. t able 25: d evice /p art n umber r egister - cr110 (a ddress l ocation = 0 x 6e) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 part number id value r/o r/o r/o r/o r/o r/o r/o r/o 0 1 0 1 1 0 0 0 register - cr110 (address location = 0x6e) b it n umber n ame t ype d efault v alue d escription 7 - 0 part number id value r/o 0x58 part number id value: this read-only register contains a unique value for the xrt75r12d. this value will always be 0x58. xrt75r12d 65 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 26: c hip r evision n umber r egister - cr111 (a ddress l ocation = 0 x 6f) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 chip revision number value r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0 x x x x register - cr111 (address location = 0x6f b it n umber n ame t ype d efault v alue d escription 7 - 0 chip revision number value r/o 0x0# chip revision number value: this read-only register contains a value that represents the current revision of this xrt75r12d. this revision num - ber will always be in the form of "0x0#", where "#" is a hexa - decimal value that specifies the current revision of the chip. for example, the very first revision of this chip will contain the value "0x01". xrt75r12d 66 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer the per-channel registers the xrt75r12d consists of 120 per-channel regist ers (12 channels and 10 registers per channel). table 27 presents the overall register map with the per-channel registers unshaded. register description - per channel registers t able 27: xrt75r12d r egister map showing i nterrupt e nable r egisters (ier_ n ) a ddress l ocation 0123456789abcdef 0x0- apst ier0 isr0 as0 tc0 rc0 cc0 ja0 apsr em0 el0 eh0 0 x 1- ier1 isr1 as1 tc1 rc1 cc1 ja1 em1 el1 eh1 0x2- ier2 isr2 as2 tc2 rc2 cc2 ja2 em2 el2 eh2 0x3- ier3 isr3 as3 tc3 rc3 cc3 ja3 em3 el3 eh3 0x4- ier4 isr4 as4 tc4 rc4 cc4 ja4 em4 el4 eh4 0x5- ier5 isr5 as5 tc5 rc5 cc5 ja5 em5 el5 eh5 0x6- cie cis pn vn 0x7- 0x8- apst ier6 isr6 as6 tc6 rc6 cc6 ja6 apsr em6 el6 eh6 0 x 9- ier7 isr7 as7 tc7 rc7 cc7 ja7 em7 el7 eh7 0xa- ier8 isr8 as8 tc8 rc8 cc8 ja8 em8 el8 eh8 0xb- ier9 isr9 as9 tc9 rc9 cc9 ja9 em9 el9 eh9 0xc- ier10 isr10 as10 tc10 rc10 cc10 ja10 em10 el10 eh10 0xd- ier11 isr11 as11 tc11 rc11 cc11 ja11 em11 el11 eh11 0xe- cie cis 0xf- xrt75r12d 67 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 28: s ource l evel i nterrupt e nable r egister - c hannel n a ddress l ocation = 0 xm 1 ( m = 0-5 & 8-d) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved change of fl condition interrupt enable ch n change of lol condition interrupt enable ch n change of los condition interrupt enable ch n change of dmo condition interrupt enable ch n r/w r/w r/w r/w b it n umber n ame t ype d escription 7 - 4 reserved r/o 3 change of fl condition interrupt enable - ch n r/w change of fl (fifo limit alarm) condition interrupt enable - ch n: this read/write bit-field is used to enable or disable the change of fifo limit alarm condition inte rrupt. if the user enabl es this interrupt, the xrt75r12d will generate an interrupt if any of the following events occur. ? whenever the jitter attenuator (within channel n) declares the fl (fifo limit alarm) condition. ? whenever the jitter atte nuator (within channel n) clears the fl (fifo limit alarm) condition. 0 - disables the change in fl condition interrupt. 1 - enables the change in fl condition interrupt. 2 change of lol condition interrupt enable r/w change of receive lol (loss of lock) condition interrupt enable - channel n: this read/write bit-field is used to enable or disable the change of receive lol condition interrupt. if the user enables this interrupt, then the xrt75r12d will generate an interrupt any time any of the following events occur. ? whenever the receive section (within channel n) declares the loss of lock condition. ? whenever the receive section (within channel n) clears the loss of lock condition. 0 - disables the change in re ceive lol condition interrupt. 1 - enables the change in re ceive lol condition interrupt. xrt75r12d 68 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 1 change of los condition interrupt enable r/w change of the receive los (loss of signal) defect co ndition interrupt enable - ch 0: this read/write bit-field is used to enable or disable the change of the receive los defect condition interrupt. if the user enables this interrupt, then the xrt75r12d will generate an interrupt any time any of the following events occur. ? whenever the receive section (within channel n) declares the los defect condition. ? whenever the receive section (withi n channel n) clears the los defect condition. 0 - disables the change in the los defect condition interrupt. 1 - enables the change in the los defect condition interrupt. 0 change of dmo condition interrupt enable r/w change of transmit dmo (drive mo nitor output) cond ition interrupt enable - ch n: this read/write bit-field is used to enable or disable the change of transmit dmo condition interrupt. if the user enables this interrupt, then the xrt75r12d will generate an interrupt any time any of the following events occur. ? whenever the transmit section toggles the dmo output pin (or bit-field) to "1". ? whenever the transmit section toggles the dmo output pin (or bit-field) to "0". 0 - disables the change in the dmo condition interrupt. 1 - enables the change in the dmo condition interrupt. b it n umber n ame t ype d escription xrt75r12d 69 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 29: xrt75r12d r egister map showing a larm s tatus r egisters (as_ n ) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved loss of prbs pattern sync digital los defect declared analog los defect declared fl (fifo limit) alarm declared receive lol defect declared receive los defect declared transmit dmo condition r/o r/o r/o r/o r/o r/o r/o source level interrupt status register - channel n address location = 0xm2 b it n umber n ame t ype d escription 7 - 4 reserved 3 change of fl con - dition interrupt sta - tus rur change of fl (fifo limit alarm) condition interrupt status - ch n: this reset-upon-read bit-field indicate s whether or not the change of fl condition interrupt (for channel n) ha s occurred since the last read of this register. 0 - indicates that the change of fl condition interrupt has not occurred since the last read of this register. 1 - indicates that the change of fl condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the fifo alarm condition by reading out the conten ts of bit 3 (fl alarm declared) within the alarm status register.(n) 2 change of lol con - dition interrupt sta - tus rur change of receive lol (loss of lock) condition interrupt status - ch n: this reset-upon-read bit-field indica tes whether or not the change of receive lol condition interrupt (for ch annel n) has occurred since the last read of this register. 0 - indicates that the change of rece ive lol condition interrupt has not occurred since the last read of this register. 1 - indicates that the change of receive lol condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the receive lol defect condition by reading out the conten ts of bit 2 (receive lol defect declared) within the alarm status register.(n) xrt75r12d 70 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 1 change of los condition interrupt status rur change of receive los (loss of si gnal) defect condition interrupt status: this reset-upon-read bit-field indica tes whether or not the change of the receive los defect condition interrupt (for channel n) has occurred since the last read of this register. 0 - indicates that the change of the re ceive los defect condition interrupt has not occurred since the last read of this register. 1 - indicates that the change of the re ceive los defect condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the receive los defect condition by reading out the contents of bit 1 (receive los defect declared) within the alarm status register.(n) 0 change of dmo condition interrupt status rur change of transmit dmo (drive mo nitor output) cond ition interrupt status - ch n: this reset-upon-read bit-field indica tes whether or not the change of the transmit dmo condition interrupt (for channel n) has occurred since the last read of this register. 0 - indicates that the change of the transmit dmo condition interrupt has not occurred since the last read of this register. 1 - indicates that the change of the transmit dmo condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the transmit dmo condition by reading out the c ontents of bit 0 (transmit dmo condition) within the alarm status register.(n) source level interrupt status register - channel n address location = 0xm2 b it n umber n ame t ype d escription xrt75r12d 71 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 30: xrt75r12 r egister map showing a larm s tatus r egisters (as_ n ) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved loss of prbs pattern sync digital los defect declared analog los defect declared fl (fifo limit) alarm declared receive lol defect declared receive los defect declared transmit dmo condition r/o r/o r/o r/o r/o r/o r/o alarm status register - cha nnel n address location = 0xm3 b it n umber n ame t ype d escription 7 reserved 6 loss of prbs pat - tern lock r/o loss of prbs pattern lock indicator: this read-only bit-field indicates whether or not the prbs receiver (within the receive section of channel n) is declaring prbs lock within the incoming prbs pattern. if the prbs receiver detects a very la rge number of bit-errors within its incoming data-stream, then it will decl are the loss of prbs lock condition. conversely, if the prbs receiver were to detect its pre-determined prbs pattern with the incoming ds3, e3 or st s-1 data-stream, (with little or no bit errors) then the prbs receiver will clear the loss of prbs lock condition. 0 - indicates that the prbs receiver is currently declaring the prbs lock condition within the incoming ds 3, e3 or sts-1 data-stream. 1 - indicates that the prbs receiver is currently declaring the loss of prbs lock condition within the incoming ds3, e3 or sts-1 data-stream. n ote : this register bit is only valid if all of the following are true. a. the prbs generator block (within the transmit section of the chip is enabled). b. the prbs receiver is enabled. c. the prbs pattern (that is generated by the prbs generator) is somehow looped back into the receive path (via the line-side) and in-turn routed to the receiv e input of the prbs receiver. xrt75r12d 72 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 5 digital los defect declared r/o digital los defect declared: this read-only bit-field indicates whether or not the digital los (loss of signal) detector is declaring the los defect condition. for ds3 and sts-1 applications, the dig ital los detector will declare the los defect condition whenever it dete cts an absence of pulses (within the incoming ds3 or sts-1 data-stream) for 160 consecutive bit-periods. further, (again for ds3 and sts-1 applic ations) the digital los detector will clear the los defect condition whenever it determines that the pulse density (within the incoming ds3 or st s-1 signal) is at least 33%. 0 - indicates that the digital los detector is not declaring the los defect condition. 1 - indicates that the digital los detector is currently declaring the los defect condition. n otes : 1. los detection (within each channel of the xrt75r12d) is performed by both an analog los detector and a digital los detector. the los state of a given channel is simply a wired- or of the los defect declare states of these two detectors. 2. the current los defect condition (for the channel) can be determined by reading out the contents of bit 1 (receive los defect declared) within this register. 4 analog los defect declared r/o analog los defect declared: this read-only bit-field indicates w hether or not the a nalog los (loss of signal) detector is declaring the los defect condition. for ds3 and sts-1 applications, the a nalog los detector will declare the los defect condition whenever it de termines that the amplitude of the pulses (within the incoming ds3/sts-1 line signal) drops below a certain analog los defect declaration threshold level. conversely, (again for ds3 and sts-1 applications) the analog los detec - tor will clear the los defect condition whenever it determines that the ampli - tude of the pulses (within the inco ming ds3/sts-1 line signal) has risen above a certain analog los defect clearance threshold level. it should be noted that, in order to prevent "chattering" within the analog los detector output, ther e is some built-in hyster esis between the analog los defect declaration and the analog los defect clearance threshold levels. 0 - indicates that the analog los dete ctor is not declaring the los defect condition. 1 - indicates that the analog los de tector is currently declaring the los defect condition. n otes : 1. los detection (within each channel of the xrt75r12d) is performed by both an analog los detector and a digital los detector. the los state of a given channel is simply a wired- or of the los defect declare states of these two detectors. 2. the current los defect condition (for the channel) can be determined by reading out the contents of bit 1 (receive los defect declared) within this register. alarm status register - cha nnel n address location = 0xm3 b it n umber n ame t ype d escription xrt75r12d 73 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 3 fl alarm declared r/o fl (fifo limit) alarm declared: this read-only bit-field indicates whether or not the jitter attenuator block (within channel_n) is currently declaring the fifo limit alarm. the jitter attenuator block will declare the fifo limit alarm anytime the jit - ter attenuator fifo comes within two bi t-periods of either overflowing or under-running. conversely, the jitter attenuator block will clear the fifo limit alarm any - time the jitter attenuator fifo is no longer within two bit-periods of either overflowing or under-running. typically, this alarm will only be declared whenever there is a very serious problem with timing or jitter in the system. 0 - indicates that the jitter attenuat or block (within channel_n) is not cur - rently declaring the fifo limit alarm condition. 1 - indicates that the jitter attenuator block (within channel_n) is currently declaring the fifo limit alarm condition. n ote : this bit-field is only active if the jitter attenuator (within channel_n) has been enabled. 2 receive lol condi - tion declared r/o receive lol (loss of lock) condition declared: this read-only bit-field indicates whether or not the receive section (within channel_n) is currently declari ng the lol (loss of lock) condition. the receive section (of channel_n) will declare the lol condition, if the frequency of the recovered clock signal differs from that of the reference clock programmed for that channel (fro m the appropriate oscillator or the sfm clock synthesizer if in that mode) by 0.5% (or 5000ppm) or more . 0 - indicates that the receive section of channel_n is not currently declar - ing the lol condition. 1 - indicates that the receive section of channel_n is currently declaring the lol condition and the recovered clock differs by more than 0.5%.. alarm status register - cha nnel n address location = 0xm3 b it n umber n ame t ype d escription xrt75r12d 74 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 1 receive los defect condition declared r/o receive los (loss of signal) defect condition declared: this read-only bit-field indicates whether or not the receive section (within channel_n) is currently dec laring the los defect condition. the receive section (of channel_n) will declare the los defect condition, if any one of the following conditions is met. ? if the digital los detector declares the los defect condition (for ds3 or sts-1 applications) ? if the analog los detector declares t he los defect condition (for ds3 or sts-1 applications) ? if the itu-t g.775 los de tector declares the los defect condition (for e3 applications). 0 - indicates that the receive section of channel_n is not currently declar - ing the los defect condition. 1 - indicates that the receive section of channel_n is currently declaring the los defect condition. 0 transmit dmo con - dition declared r/o transmit dmo (drive monitor output) condit ion declared: this read-only bit-field indicates whether or not the transmit section of channel_n is currently decla ring the dmo alarm condition. as configured, the transmit section will either internally (via the ttip_n and tring_n ) or externally (via the mt ip_n and mring_n) check the transmit output ds3/e3/sts-1 line signal for bipolar pulses. if the transmit section were to detect no bipolar for 128 consec utive bit-periods, then it will declare the transmit dmo alarm condition. this particular alarm can be used to check for fault conditions on the transmit output line signal path. the transmit section will clear the transmit dmo alarm condition upon detecting bipolar activity on the transmit output line signal. 0 - indicates that the transmit secti on of channel_n is not currently declar - ing the transmit dmo alarm condition. 1 - indicates that the transmit section of channel_n is currently declaring the transmit dmo alarm condition. alarm status register - cha nnel n address location = 0xm3 b it n umber n ame t ype d escription xrt75r12d 75 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 31: xrt75r12d r egister map showing t ransmit c ontrol r egisters (tc_ n ) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved internal transmit drive monitor insert prbs error reserved taos txclkinv txlev r/w r/w r/w r/w r/w t ransmit c ontrol r egister - c hannel n a ddress l ocation = 0 xm 4 b it n umber n ame t ype d escription 7 - 6 reserved 5 internal transmit drive monitor enable r/w internal transmit drive monitor enable - channel_n: this read/write bit-field is used to configure the transmit section of channel_n to either internally or externally monitor the ttip_n and tring_n output pins for bipolar pulses, in order to determine whether to declare the transmit dmo alarm condition. if the user configures the transmit se ction to externally monitor the ttip_n and tring_n output pins (for bipolar pulses) then the user must connect the mtip_n and mring_n input pins to their corresponding ttip_n and tring_n output pins (via a 270 ohm series resistor). if the user configures the transmit sect ion to internally monitor the ttip_n and tring_n output pins (for bipolar pulses), the user does not need to conect the mtip_n and mring_n input pins. this monitoring will be per - formed internally at the ttip_n and tring_n pads. 0 - configures the transmit drive moni tor to externally monitor the ttip_n and tring_n output pins for bipolar pulses. 1 - configures the transmit drive monitor to internally monitor the ttip_n and tring_n output pins for bipolar pulses. 4 insert prbs error r/w insert prbs error - channel_n: a "0 to 1" transition within this bit- field causes the prbs generator (within the transmit section of channel_n) to generate a single bit error within the outbound prbs pattern-stream. n otes : 1. this bit-field is only active if the prbs generator and receiver have been enabled within the corresponding channel. 2. after writing the "1" into this regi ster, the user must execute a write operation to clear this particular register bit to "0" in order to facilitate the next "0 to 1" transition in this bit-field. 3 reserved xrt75r12d 76 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 2 taos r/w transmit all ones pattern - channel_n: this read/write bit-field is used to command the transmit section of channel_n to generate and transmit an unframed, all ones pattern via the ds3, e3 or sts-1 line signal (to the remote terminal equipment). whenever the user implements this c onfiguration setting, the transmit sec - tion will ignore the data that it is a ccepting from the system-side equipment and output the "a ll ones" pattern. 0 - configures the transmit section to transmit the data that it accepts from the system-side interface. 1 - configures the transmit section to generate and transmit the unframed, all ones pattern. 1 txclkinv r/w transmit clock invert select - channel_n: this read/write bit-field is used to select the edge of the txclk_n input that the transmit section of channel_n will use to sample the txpos_n and txneg_n input pins, as described below. 0 - configures the transmit section (within the corresponding channel) to sample the txpos_n and txneg_n in put pins upon the falling edge of txclk_n. 1 - configures the transmit section (within the corresponding channel) to sample the txpos_n and txneg_n input pins upon the rising edge of txclk_n. n ote : this is done on a per-channel basis. 0 txlev r/w transmit line build-out select - channel_n: this read/write bit-field is used to enable or disable the transmit line build-out (e.g., pulse-shaping) circuit within the corresponding channel. the user should set this bit-field to either "0" or to "1" based upon the follow - ing guidelines. 0 - if the cable length between the transmit output (of the corresponding channel) and the dsx-3/stsx-1 location is 225 feet or less. 1 - if the cable length between the transmit output (of the corresponding channel) and the dsx-3/stsx-1 location is more than 225 feet . the user must follow these guidelines in order to insure that the transmit section (of channel_n) will always generate a ds3 pulse that complies with the isolated pulse template requirements per bellcore gr-499-core, or an sts-1 pulse that complies with the pulse template requirements per tel - cordia gr-253-core. n ote : this bit-field is ignored if the channel has been configured to operate in the e3 mode. t ransmit c ontrol r egister - c hannel n a ddress l ocation = 0 xm 4 b it n umber n ame t ype d escription xrt75r12d 77 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 32: xrt75r12d r egister map showing r eceive c ontrol r egisters (rc_ n ) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved disable dlos detector disable alos detector rxclkinv losmut enable receive monitor mode enable receive equalizer enable r/w r/w r/w r/w r/w r/w r eceive c ontrol r egister - c hannel n a ddress l ocation = 0 xm 5 b it n umber n ame t ype d escription 7 - 6 reserved 5 disable dlos detector r/w disable digital los detector - channel_n: this read/write bit-field is used to enable or disable the digital los (loss of signal) detector within channel_n, as described below. 0 - enables the digital los detector within channel_n. 1 - disables the digital los detector within channel_n. n ote : this bit-field is only active if channel_n has been configured to operate in the ds3 or sts-1 modes. 4 disable alos detector r/w disable analog los detector - channel_n: this read/write bit-field is used to either enable or disable the analog los (loss of signal) detector withi n channel_n, as described below. 0 - enables the analog los detector within channel_n. 1 - disables the analog los detector within channel_n. n ote : this bit-field is only active if channel_n has been configured to operate in the ds3 or sts-1 modes. 3 rxclkinv r/w receive clock invert select - channel_n: this read/write bit-field is used to select the edge of the rxclk_n out - put that the receive section of channel_n will use to output the recovered data via the rxpos_n and rxneg_n output pins, as described below. 0 - configures the receive section (within the corresponding channel) to output the recovered data via the rx pos_n and rxneg_n output pins upon the rising edge of rclk_n. 1 - configures the receive section (within the corresponding channel) to output the recovered data via the rx pos_n and rxneg_n output pins upon the falling edge of rclk_n. 2 losmut enable r/w muting upon los enable - channel_n: this read/write bit-field is used to configure the receive section (within channel_n) to automatically pull their corresponding recovered data out - put pins (e.g., rxpos_n and rxneg_n) to gnd for the duration that the receive section declares the los defect condition. in other words, this fea - ture (if enabled) will cause the receiv e channel to automatically mute the recovered data anytime the receive se ction declares t he los defect con - dition. 0 - disables the muting upon los feature. in this setting the receive sec - tion will not automatically mute the recovered data whenever it is declar - ing the los defect condition. 1 - enables the muting upon los feature. in this setting the receive sec - tion will automatically mute the recovered data whenever it is declaring the los defect condition. xrt75r12d 78 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 1 receive monitor mode enable r/w receive monitor mode enable - channel_n: this read/write bit-field is used to configure the receive section of channel_n to operate in the receive monitor mode. if the user configures the receive sect ion to operate in the receive monitor mode, then it will be able to receive a nominal dsx-3/stsx-1 signal that has been attenuated by 20db of flat lo ss along with 6db of cable loss, in an error-free manner. however, internal los circuitry is suppressed and los will never assert nor los be declared when operating under this mode. 0 - configures the corresponding channel to operate in the normal mode. 1 - configure the corresponding channel to operate in the receive monitor mode. 0 receive equalizer enable r/w receive equalizer enable - channel_n: this read/write register bit is used to enable or disable the receive equalizer block within the receive section of channel_n, as listed below. 0 - disables the receive equalizer within the corresponding channel. 1 - enables the receive equalizer within the corresponding channel. n ote : for virtually all applications, we recommend that the user set this bit- field to "1" (for all channels) and enable the receive equalizer. r eceive c ontrol r egister - c hannel n a ddress l ocation = 0 xm 5 b it n umber n ame t ype d escription xrt75r12d 79 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 t able 33: xrt75r12d r egister map showing c hannel c ontrol r egisters (cc_ n ) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved prbs enable ch_n rlb_n llb_n e3_n sts-1/ ds3 _n sr/ dr _n r/w r/w r/w r/w r/w r/w c hannel c ontrol r egister - c hannel n a ddress l ocation = 0 xm 6 b it n umber n ame t ype d escription 7 - 6 reserved 5 prbs enable r/w prbs generator and receiver enable - channel_n: this read/write bit-field is used to enable or disable the prbs generator and receiver within a given channel of the xrt75r12d. if the user enables the prbs generator and receiver, then the following will happen. 1. the prbs generator (which resides within the transmit section of the channel) will begin to generate an unframed, 2^15-1 prbs pattern (for ds3 and sts-1 appl ications) and an unframed, 2^23-1 prbs pattern (for e3 applications). 2. the prbs receiver (which resides within the receive section of the channel) will now be enabled and will begin to search the incoming data for the above-mentioned prbs patterns. 0 - disables both the prbs generator and prbs receiver within the corre - sponding channel. 1 - enables both the prbs generator and prbs receiver within the corre - sponding channel. n otes : 1. to check and monitor prbs bit errors, dr (dual rail) mode will be over-ridden and single rail mode forced for the duration of this mode. this will configure the rneg/ lcv_n output pin to function as a prbs error indicator. all errors will be flagged on this pin. the errors will also be accumulated in the 16 bit error counter for the channel. 2. if the user enables the prbs generator and prbs receiver, the channel will ignore the data that is being accepted from the system-side equipment (via th e txpos_n and txneg_n input pins) and will overwrite this out bound data with the prbs pattern. 3. the system must provide an accura te and stable data-rate clock to the txclk_n pin during this operation. xrt75r12d 80 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 4 rlb_n r/w loop-back select - rlb bit - channel_n: this read/write bit-field along with the corresponding llb_n bit-field is used to configure a given channel into various loop-back modes ass shown by the following table. 3 llb_n r/w loop-back select - llb bit-field - channel_n: see the table (above) for rlb_n. 2 e3_n r/w e3 mode select - channel_n: this read/write bit-field, along with bit 1 (sts-1/ ds3 _n) within this reg - ister, is used to configure a given channel into either the ds3, e3 or sts-1 modes. 0 - configures channel_n to operate in either the ds3 or sts-1 modes, depending upon the state of bit 1 (sts-1/ ds3 _n) within this same register. 1- configures channel_n to operate in the e3 mode. c hannel c ontrol r egister - c hannel n a ddress l ocation = 0 xm 6 b it n umber n ame t ype d escription loop-back mode digital local loop-back mode analog local loop-back mode remote loop-back mode normal (no loop-back) mode rlb_n 1 0 1 0 llb_n 1 1 0 0 xrt75r12d 81 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 1 sts-1/ ds3 _n r/w sts-1/ds3 mode select - channel_n: this read/write bit-field, along with bit 2 (e3_n) is used to configure a given channel into either the ds3, e3 or sts-1 modes. this bit-field is ignored if bit 2 (e3_n) has been set to "1". if bit 2 (e3_n) is a 0: 0 - configures channel_n to operate in the ds3 mode. 1 - configures channel_n to operate in the sts-1 mode . 0 sr/ dr _n r/w single-rail/dual-rail select - channel_n: this read/write bit-field is used to configure channel_n to operate in either the single-rail or dual-rail mode. if the user configures the channel to operate in the single-rail mode, the following will happen. ? the b3zs/hdb3 encoder and decoder blocks (within channel_n) will be enabled. ? the transmit section of channel_n will accept all of the outbound data (from the system-side equipment) via the txpos_n input pin. ? the receive section of each channel will output all of the recovered data (to the system-side equipment) via the rxpos_n output pin. ? the corresponding rneg/lcv_n output pin will now function as the lcv (line code violation or excessive zero event) indicator output pin for channel_n. if the user configures channel_n to operate in the dual-rail mode, the fol - lowing will happen. ? the b3zs/hdb3 encoder and decode r blocks of chann el_n will be disabled. ? the transmit section of channel_n will be configured to accept positive- polarity data via the txpos_n input pin and negative-polarity data via the txneg_n input pin. ? the receive section of channel_n will pulse the rxpos_n output pin "high" (for one period of rclk_n) for each time a positive-polarity pulse is received via the rtip_n/rring_n inpu t pins. likewise, the receive section of each channel will pulse the rxneg_n output pin "high" (for one period of rxclk_n) for each time a negative-polarity pulse is received via the rtip_n/rring_n input pins. 0 - configures channel_n to operate in the dual-rail mode. 1 - configures channel_n to operate in the single-rail mode. t able 34: xrt75r12d r egister map showing j itter a ttenuator c ontrol r egisters (ja_ n ) b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 reserved ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/w r/w r/w r/w c hannel c ontrol r egister - c hannel n a ddress l ocation = 0 xm 6 b it n umber n ame t ype d escription xrt75r12d 82 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer t able 35: xrt75r12d r egister map showing e rror c ounter msb yte r egisters (em_ n ) j itter a ttenuator c ontrol r egister - c hannel n a ddress l ocation = 0 xm 7 b it n umber n ame t ype d escription 7 - 4 reserved 3 ja reset ch_n r/w jitter attenuator reset - channel_n: writing a "0 to 1" transition within this bit-field will configure the jitter attenu - ator (within channel_n) to execute a reset operation. whenever the user executes a reset operation, then following will occur. ? the read and write pointers (within the jitter attenuator fifo) will be reset to their default values. ? the contents of the jitter at tenuator fifo will be flushed. n ote : the user must follow up any "0 to 1" transition with the appropriate write operate to set this bit-field back to "0", in order to resume normal operation with the jitter attenuator. 2 ja1 ch_n r/w jitter attenuator configuration select input - bit 1: this read/write bit-field, along with bit 0 (ja0 ch_n) is used to do any of the following. ? to enable or disable the jitter attenuator corresponding to channel_n. ? to select the fifo depth for the jitter attenuator within channel_n. the relationship between the settings of these two bit-fields and the enable/ disable states, and fifo d epths is presented below. 1 ja in tx path ch_n r/w jitter attenuator in transmit/receive path select bit: this input pin is used to configure the jitter attenuator (within channel_n) to operate in either the transmit or receive path, as described below. 0 - configures the jitter attenuator (within channel_n) to operate in the receive path. 1 - configures the jitter attenuator (within channel_n) to operate in the transmit path. 0 ja0 ch_n r/w jitter attenuator configuration select input - bit 0: see the description for bit 2 (ja1 ch_n). a ddress l ocation 0123456789abcdef 0x0- apst ier0 isr0 as0 tc0 rc0 cc0 ja0 apsr em0 el0 eh0 0 x 1- ier1 isr1 as1 tc1 rc1 cc1 ja1 em1 el1 eh1 0x2- ier2 isr2 as2 tc2 rc2 cc2 ja2 em2 el2 eh2 ja0 ja1 jitter attenuator mode 1 1 disabled 1 0 disabled 0 1 fifo depth = 32 bits 0 0 fifo depth = 16 bits xrt75r12d 83 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 0x3- ier3 isr3 as3 tc3 rc3 cc3 ja3 em3 el3 eh3 0x4- ier4 isr4 as4 tc4 rc4 cc4 ja4 em4 el4 eh4 0x5- ier5 isr5 as5 tc5 rc5 cc5 ja5 em5 el5 eh5 0x6- cie cis pn vn 0x7- 0x8- apst ier6 isr6 as6 tc6 rc6 cc6 ja6 apsr em6 el6 eh6 0 x 9- ier7 isr7 as7 tc7 rc7 cc7 ja7 em7 el7 eh7 0xa- ier8 isr8 as8 tc8 rc8 cc8 ja8 em8 el8 eh8 0xb- ier9 isr9 as9 tc9 rc9 cc9 ja9 em9 el9 eh9 0xc- ier10 isr10 as10 tc10 rc10 cc10 ja10 em10 el10 eh10 0xd- ier11 isr11 as11 tc11 rc11 cc11 ja11 em11 el11 eh11 0xe- cie cis 0xf- t able 36: e rror c ounter msb yte r egister - c hannel n a ddress l ocation = 0 xm a b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 msb 9th bit r/w r/w r/w r/w r/w r/w r/w r/w t able 37: xrt75r12d r egister map showing e rror c ounter lsb yte r egisters (el_ n ) a ddress l ocation 0123456789abcdef 0x0- apst ier0 isr0 as0 tc0 rc0 cc0 ja0 apsr em0 el0 eh0 0 x 1- ier1 isr1 as1 tc1 rc1 cc1 ja1 em1 el1 eh1 0x2- ier2 isr2 as2 tc2 rc2 cc2 ja2 em2 el2 eh2 0x3- ier3 isr3 as3 tc3 rc3 cc3 ja3 em3 el3 eh3 0x4- ier4 isr4 as4 tc4 rc4 cc4 ja4 em4 el4 eh4 0x5- ier5 isr5 as5 tc5 rc5 cc5 ja5 em5 el5 eh5 0x6- cie cis pn vn 0x7- 0x8- apst ier6 isr6 as6 tc6 rc6 cc6 ja6 apsr em6 el6 eh6 0 x 9- ier7 isr7 as7 tc7 rc7 cc7 ja7 em7 el7 eh7 0xa- ier8 isr8 as8 tc8 rc8 cc8 ja8 em8 el8 eh8 0xb- ier9 isr9 as9 tc9 rc9 cc9 ja9 em9 el9 eh9 a ddress l ocation 0123456789abcdef xrt75r12d 84 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 0xc- ier10 isr10 as10 tc10 rc10 cc10 ja10 em10 el10 eh10 0xd- ier11 isr11 as11 tc11 rc11 cc11 ja11 em11 el11 eh11 0xe- cie cis 0xf- t able 38: e rror c ounter lsb yte r egister - c hannel n a ddress l ocation = 0 xm b b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 8th bit ls bit r/w r/w r/w r/w r/w r/w r/w r/w t able 39: xrt75r12d r egister map showing e rror c ounter h olding r egisters (eh_ n ) a ddress l ocation 0123456789abcdef 0x0- apst ier0 isr0 as0 tc0 rc0 cc0 ja0 apsr em0 el0 eh0 0 x 1- ier1 isr1 as1 tc1 rc1 cc1 ja1 em1 el1 eh1 0x2- ier2 isr2 as2 tc2 rc2 cc2 ja2 em2 el2 eh2 0x3- ier3 isr3 as3 tc3 rc3 cc3 ja3 em3 el3 eh3 0x4- ier4 isr4 as4 tc4 rc4 cc4 ja4 em4 el4 eh4 0x5- ier5 isr5 as5 tc5 rc5 cc5 ja5 em5 el5 eh5 0x6- cie cis pn vn 0x7- 0x8- apst ier6 isr6 as6 tc6 rc6 cc6 ja6 apsr em6 el6 eh6 0 x 9- ier7 isr7 as7 tc7 rc7 cc7 ja7 em7 el7 eh7 0xa- ier8 isr8 as8 tc8 rc8 cc8 ja8 em8 el8 eh8 0xb- ier9 isr9 as9 tc9 rc9 cc9 ja9 em9 el9 eh9 0xc- ier10 isr10 as10 tc10 rc10 cc10 ja1 0 em10 el10 eh10 0xd- ier11 isr11 as11 tc11 rc11 cc11 ja11 em11 el11 eh11 0xe- cie cis 0xf- t able 37: xrt75r12d r egister map showing e rror c ounter lsb yte r egisters (el_ n ) a ddress l ocation 0123456789abcdef xrt75r12d 85 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 each channel contains a ded icated 16 bit prbs error counter. when enabled this coun ter will accumulate prbs errors (as well as excess zeros and lcvs). the ls byte will "carry" a one over to the ms byte each time it rolls over from 255 to zero until the ms byte also reaches 255. when both counters reach 255, no further errors will be accu mulated and "all ones" will si gnify an overflow condition. the counter can be read while in the active count mode. either register may be read "on the fly" and the other byte will be simultaneously tr ansferred into the channel?s error holding register. the holding register may then be read to supply the host with a correct 16 bit count (as of the instant of reading). with this mechanism, the host could rapidly cycle thru reading all twelve counters in order (storing the read byte in scratch ram) and then come back and read the second byte from each holding register to form the 16 bit accumulation in the host system. t able 40: e rror c ounter h olding r egister - c hannel n a ddress l ocation = 0 xm c b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 msb ls bit r/w r/w r/w r/w r/w r/w r/w r/w xrt75r12d 86 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 8.0 the sonet/sdh de-sync function within the liu the liu with d-sync is very similar to the non d-sync liu in that they both contain jitter attenuator blocks within each channel. they are also pin to pin compatib le with each other. however, the jitter attenuators within the d-sync have some enhancements over and abo ve those within the non d-sync device. the jitter attenuator blocks will sup port all of the mo des and features that exist in the non d- sync device and in addition they also support a sonet/sdh de-sync mode. n ote : the "d" suffix within the part number stands for "de-sync". the sonet/sdh de-sync feature of the jitter attenua tor blocks permits the user to design a sonet/sdh pte (path terminating equipment) that will comply with all of the follo wing intrinsic jitter and wander requirements. ? for sonet applications category i intrinsic jitter requirements per telcordia gr-253-core (for ds3 applications) ansi t1.105.03b-1997 - sonet jitter at ne twork interfaces - ds3 wander supplement ? for sdh applications jitter and wander generation requirements per itu-t g.783 (for ds3 and e3 applications) specifically, if the user designs in the liu along with a sonet/sdh mapper ic (which can be realized as either a standard product or as a custom logic solution, in an asic or fpga), then the following can be accomplished. ? the mapper can receive an sts-n or an stm-m signal (which is carrying asynchronously-mapped ds3 and/ or e3 signals) and byte de-interleave this data into n sts-1 or 3*m vc-3 signals ? the mapper will then terminate these sts-1 or vc-3 signals and w ill de-map out this ds3 or e3 data from the incoming sts-1 spes or vc-3s, an d output this ds3 or e3 to the ds 3/e3 facility-side towards the liu ? this ds3 or e3 signal (as it is output from these mapper devices) will cont ain a large amount of intrinsic jitter and wander due to (1) the process of asynchronously mapping a ds3 or e3 signal into a sonet or sdh signal, (2) the occurrence of pointer adjustments with in the sonet or sdh signal (transporting these ds3 or e3 signals) as it traverses the so net/sdh network, and (3) clock gapping. ? when the liu has been configured to operate in the "sonet/sdh de-sync" mode, then it will (1) accept this jittery ds3 or e3 clock and data signal from the mapper device (via the transmit system-side interface) and (2) through the jitter attenua tor, the liu will reduce the jitter and wander amplitude within these ds3 or e3 signals such that they (when output onto the line) will comply with the above-mentioned intrinsic jitter and wander specifications. 8.1 background and detailed information - sonet de-sync applications this section provides an in -depth discussion on the mechanisms th at will cause jitter and wander within a ds3 or e3 signal that is being transported across a so net or sdh network. a lot of this material is introductory, and can be skipped by the engineer that is already experienced in sonet/sdh designs. in the wide-area network (wan) in north america it is often necessary to transport a ds3 signal over a long distance (perhaps over a thousand miles) in order to support a particular service. now rather than realizing this transport of ds3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of ds3 repeaters) a common thing to do is to route this ds 3 signal to a piece of equipment (such as a terminal mux, which in the "sonet community" is known as a pte or path terminating equipment). this terminal mux will asynchronously ma p the ds3 signal into a sonet signal. at this point, the sonet network will now transport this asynchronously mapped ds3 signal from one pte to another pte (which is located at the other end of the sonet network). once this sonet signal arrives at the remote pte, this ds3 signal will then be extracted from the sonet signal, and will be output to some other ds3 terminal equipment for further processing. similar things are done outside of north america. in this case, this ds3 or e3 signal is routed to a pte, where it is asynchronously mapped into an sdh signal. th is asynchronously mapped ds3 or e3 signal is then xrt75r12d 87 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 transported across the sdh network (from one pte to the pte at the other end of the sdh network). once this sdh signal arrives at the remote pte, this ds3 or e3 signal will then be extr acted from the sdh signal, and will be output to some other ds3/e3 terminal equi pment for further processing. figure 37 presents an illustration of this approach to transporting ds 3 data over a sonet network as mentioned above a ds3 or e3 signal will be asynch ronously mapp ed into a sonet or sdh signal and then transported over the so net or sdh network. at the remote pte th is ds3 or e3 signal will be extracted (or de-mapped) from this sonet or sdh si gnal, where it will then be routed to ds3 or e3 terminal equipment for further processing. in order to insure that this "de-mapped" ds3 or e3 si gnal can be routed to any industry-standard ds3 or e3 terminal equipment, without any complications or adve rse effect on the network, the telcordia and itu-t standard committees have specified some limits on both th e intrinsic jitter and wan der that may exist within these ds3 or e3 signals as they are de-mapped from so net/sdh. as a consequence, all ptes that maps and de-mapped ds3/e3 signals into/from sonet/sdh must be designed such that the ds3 or e3 data that is de-mapped from sonet/sdh by these ptes must meet these intrinsic jitter and wander requirements. as mentioned above, the liu can assist the system de signer (of sonet/sdh pte) by ensuring that their design will meet these intrinsic ji tter and wander requirements. this section of the data s heet will present the following information to the user. ? some background information on mapping ds3/e3 signals into sonet/sdh and de-mapping ds3/e3 signals from sonet/sdh. ? a brief discussion on the causes of jitter and wander within a ds3 or e3 signal that mapped into a sonet/ sdh signal, and is transported across the sonet/sdh network. ? a brief review of these intrinsic jitter and wander requirements in both sonet and sdh applications. ? a brief review on the intrinsic jitter and wander measurement results (of a de-mapped ds3 or e3 signal) whenever the liu device is used in a system design. f igure 37. a s imple i llustration of a ds3 signal being mapped into and transported over the sonet n etwork pte pte pte pte sonet network ds3 data ds3 data xrt75r12d 88 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer ? a detailed discussion on how to design with and confi gure the liu device such th at the end-system will meet these intrinsic jitter and wander requirements. in a sonet system, the relevant specification requirem ents for intrinsic jitter and wander (within a ds3 signal that is mapped into and then de-mapped from sonet) are listed below. ? telcordia gr-253-core category i in trinsic jitter requirements for ds3 applications (section 5.6), and ? ansi t1.105.03b-1997 - sonet jitter at ne twork interfaces - ds3 wander supplement in general, there are three (3) sources of jitter and wander within an asynchronously-mapped ds3 signal that the system designer must be aware of. these sources are listed below. ? mapping/de-mapping jitter ? pointer adjustments ? clock gapping each of these sources of jit ter/wander will be defined and discussed in considerable detail wi thin this section. in order to accomplish all of this, th is particular section will discuss all of the following topics in details. ? how ds3 data is mapped into sonet, and how this mapping operation contributes to jitter and wander within this "eventually de-mapped" ds3 signal. ? how this asynchronously-mapped ds3 data is tran sported throughout the sonet network, and how occurrences on the sonet network (such as pointer adjustments) will further contributes to jitter and wander within the "eventually de-mapped" ds3 signal. ? a review of the category i intrinsi c jitter requirements (per telcordia gr-253-core) for ds3 applications ? a review of the ds3 wander requirements per ansi t1.105.03b-1997 ? a review of the intrinsic jitter and wander capabilities of the liu in a typical system application ? an in-depth discussion on how to design with and co nfigure the liu to permit the system to the meet the above-mentioned intrinsic jitter and wander requirements n ote : an in-depth discussion on sdh de-sync applications will be presented in the next revision of this data sheet. 8.2 mapping/de-mapping jitter/wander mapping/de-mapping jitter (or wander) is defined as that intrinsic jitter (or wander) th at is induced into a ds3 signal by the "asynchronous mapping" process. this section will discuss all of the following aspects of mapping/de-mapping jitter. ? how ds3 data is mapped into an sts-1 spe ? how frequency offsets within either the ds3 signal (being mapped into sonet) or within the sts-1 signal itself contributes to intrinsic jitte r/wander within the ds3 signal (being transported via the sonet network). 8.2.1 how ds3 data is mapped into sonet whenever a ds3 signal is asynchronously mapped into sonet, this mapping is typically accomplished by a pte accepting ds3 data (from some remote terminal) and then loading this data into certain bit-fields within a given sts-1 spe (or sy nchronous payload en velope). at this point, th is ds3 signal has now been asynchronously mapped into an sts-1 signal. in most applications, the sone t network will then take this particular sts-1 signal and will map it into "higher-sp eed" sonet signals (e.g., st s-3, sts-12, sts-48, etc.) and will then transport this asynchronously m apped ds3 signal across the sonet network, in this manner. as this "asynchronously-ma pped" ds3 signal approaches its "destinatio n" pte, this sts-1 signal will eventually be de-mapped from this sts-n signal. finally, once this sts-1 signal reaches the "destination" pte, then this asynchronously-mapped ds3 signal will be extracted from this sts-1 signal. 8.2.1.1 a brief descript ion of an sts-1 frame xrt75r12d 89 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 in order to be able to desc ribe how a ds3 signal is asynchronously m apped into an sts-1 spe, it is important to define and understand all of the following. ? the sts-1 frame structure ? the sts-1 spe (synchron ous payload envelope) ? telcordia gr-253-core's recommendation on mapping ds3 data into an sts-1 spe an sts-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). a given sts-1 frame can be viewed as being a 9 row by 90 byte column array (maki ng up the 810 bytes). the frame-repetition rate (for an sts-1 frame) is 8000 frames/second. therefore, the bit-rate for an sts-1 signal is (6480 bits/frame * 8000 frames/sec =) 51.84mbps. a simple illustration of this sonet sts-1 frame is pr esented below in figure 38 . figure 38 indicates that the very first byte of a given sts-1 frame (to be transmitted or received) is located in the extreme upper left hand corner of the 90 column by 9 row array, and that the very last byte of a given sts- 1 frame is located in the extreme lower right-hand corner of the frame structure. whenever a network element transmits a sonet sts-1 frame, it starts by transmitting all of the data, residing within the top row of the sts- 1 frame structure (beginning with the left-most byte, and then transmitting the very next byte, to the right). after the network equipment has completed its transmission of the top or first row, it will then proceed to transmit the second row of data (again starting with the left-most byte, first). once the network equipment has transmitted the last byte of a given sts-1 fr ame, it will proceed to start tran smitting the very next sts-1 frame. the illustration of the sts-1 frame (in figure 38 ) is very simplistic, for multiple reasons. one major reason is that the sts-1 frame consists of numerous types of bytes. for the sake of discussion within this data sheet, the sts-1 frame will be described as consisting of the following types (or groups) of bytes. ? the transport overheads (or toh) bytes ? the envelope capacity bytes 8.2.1.1.1 the transport overhead (toh) bytes the transport overhead or toh bytes occupy the very fi rst three (3) byte columns within each sts-1 frame. figure 39 presents another simple illustration of an sts-1 fr ame structure. however, in this case, both the toh and the envelope capacity bytes are designated in this figure. f igure 38. a s imple i llustration of the sonet sts-1 f rame sts-1 frame (810 bytes) 90 bytes 9 rows first byte of the sts-1 frame last byte of the sts-1 frame xrt75r12d 90 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer since the toh bytes occupy the first three byte column s of each sts-1 frame, and since each sts-1 frame consists of nine (9) rows, then we can state that the to h (within each sts-1 frame) consists of 3 byte columns x 9 rows = 27 bytes. the byte format of the toh is presented below in figure 40 . f igure 39. a s imple i llustration of the sts-1 f rame s tructure with the toh and the e nvelope c apacity b ytes d esignated toh envelope capacity 87 bytes 3 bytes 90 bytes 9 row xrt75r12d 91 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 in general, the role/purpose of the toh bytes is to fu lfill the following functions. ? to support sts-1 frame synchronization ? to support error detection within the sts-1 frame ? to support the transmission of various alarm conditions such as rdi-l (line - remote defect indicator) and rei-l (line - remote error indicator) ? to support the transmission and re ception of "section trace" messages ? to support the transmission and reception of oam &p messages via the dcc bytes (data communication channel bytes - d1 through d12 byte) the roles of most of the toh bytes is beyond the scope of this data sheet and w ill not be discussed any further. however, there are a three toh bytes that are important from the stand-point of this data sheet, and will discussed in considerable detail throughout this document. these are the h1 and h2 (e.g., the spe pointer) bytes and the h3 (e.g ., the pointer action) byte. figure 41 presents an illustration of the byte-format of the toh within an sts-1 frame, with the h1, h2 and h3 bytes highlighted. f igure 40. t he b yte -f ormat of the toh within an sts-1 f rame a1 a1 b1 b1 d1 d1 h1 h1 b2 b2 d4 d4 s1 s1 d10 d10 d7 d7 c1 c1 f1 f1 d3 d3 h3 h3 k2 k2 d6 d6 e2 e2 d12 d12 d9 d9 a2 a2 e1 e1 d2 d2 h2 h2 k1 k1 d5 d5 m0 m0 d11 d11 d8 d8 envelope capacity bytes envelope capacity bytes 3 byte columns 87 byte columns 9 rows the toh bytes xrt75r12d 92 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer although the role of the h1, h2 and h3 bytes will be discussed in much greater detail in ?section 8.3, jitter/ wander due to pointer adjustments? on page 99 . for now, we will simply stat e that the role of these bytes is two-fold. ? to permit a given pte (path terminating equipment) that is receiving an sts-1 data to be able to locate the sts-1 spe (synchronous payload enve lope) within the envel ope capacity of this incoming sts-1 data stream and, ? to inform a given pte whenever pointer adjustment and ndf (new data flag) events occur within the incoming sts-1 data-stream. 8.2.1.1.2 the envelope capacity bytes within an sts-1 frame in general, the envelope capacity bytes are any bytes (within an sts-1 frame) that exist outside of the toh bytes. in short, the envelope capacity contains the sts-1 spe (synchronous payload envelope). in fact, every single byte that exists within the envelope capacity also exists within the sts-1 spe. the only difference that exists between the "envelope capacity" as defined in figure 40 and figure 41 above and the sts-1 spe is that the envelo pe capacity is aligned with the sts-1 framing boundaries and the toh bytes; whereas the sts-1 spe is not alig ned with the sts-1 framing boun daries, nor the toh bytes. the sts-1 spe is an "87 byte column x 9 row" data-structure (which is the exact same size as is the envelope capacity) that is permitted to "float " within the "envelope capacity". as a consequence, t he sts-1 spe (within an sts-1 data-stream) will typically st raddle across an sts-1 frame boundary. 8.2.1.1.3 the byte structure of the sts-1 spe as mentioned above, the sts-1 spe is an 87 byte column x 9 ro w structure. the very first column within the sts-1 spe consists of some overhead bytes which are known as the "pat h overhead" (or poh) bytes. the remaining portions of the sts-1 spe is available for "user" data. the byte structure of the sts-1 spe is presented below in figure 42 . f igure 41. t he b yte -f ormat of the toh within an sts-1 f rame a1 a1 b1 b1 d1 d1 h1 h1 b2 b2 d4 d4 s1 s1 d10 d10 d7 d7 c1 c1 f1 f1 d3 d3 h3 h3 k2 k2 d6 d6 e2 e2 d12 d12 d9 d9 a2 a2 e1 e1 d2 d2 h2 h2 k1 k1 d5 d5 m0 m0 d11 d11 d8 d8 envelope capacity bytes envelope capacity bytes 3 byte columns 87 byte columns 9 rows the toh bytes xrt75r12d 93 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 in general, the role/purpose of the poh by tes is to fulfill the following functions. ? to support error detection within the sts-1 spe ? to support the transmission of various alarm conditions such as rdi-p (path - remo te defect indicator) and rei-p (path - remote error indicator) ? to support the transmission and re ception of "path trace" messages the role of the poh bytes is beyond the scope of this data sheet and will not be discussed any further. 8.2.1.2 mapping ds3 data into an sts-1 spe now that we have defined the sts-1 spe, we can now describe how a ds3 signal is mapped into an sts-1 spe. as mentioned abov e, the sts-1 spe is basically an 87 byte column x 9 row stru cture of data. the very first byte column (e.g., in all 9 bytes) consists of the poh (path over head) bytes. all of the remaining bytes within the sts-1 spe is simply referred to as "user" or "payload" data because this is the portion of the sts-1 signal that is used to transport "user data" from one en d of the sonet network to the other. telcordia gr-253- core specifies the approach that on e must use to asynchronously map ds3 data into an sts-1 spe. in short, this approach is presented below in figure 43 . f igure 42. i llustration of the b yte s tructure of the sts-1 spe z5 z5 z4 z4 z3 z3 h4 h4 f2 f2 g1 g1 c2 c2 b3 b3 j1 j1 payload (or user) data 86 bytes 1 byte 87 bytes 9 rows xrt75r12d 94 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer figure 43 was copied directly out of telcordia gr-253-cor e. however, this figure can be simplified and redrawn as depicted below in figure 44 . f igure 43. a n i llustration of t elcordia gr-253-core' s r ecommendation on how map ds3 data into an sts-1 spe f igure 44. a s implified "b it -o riented " v ersion of t elcordia gr-253-core' s r ecommendation on how to map ds3 data into an sts-1 spe ? for ds3 mapping, the sts-1 spe has the following structure. 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r poh 87 bytes r = [r, r, r, r, r, r, r, r] i = [i, i, i, i, i, i, i, i] c1 = [r, r, c, i, i, i, i, i] c2 = [c, c, r, r, r, r, r, r] c3 = [c, c, r, r, o, o, r, s] i = ds3 data r = fixed stuff bit c = stuff control bit s = stuff opportunity bit o = overhead communications channel bit fixed stuff 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r r c s i o - fixed stuff bits - stuff control/indicator bits - ds3 data bits - stuff opportunity bits - overhead communication bits poh xrt75r12d 95 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 figure 44 presents an alternat ive illustration of telcordia gr-253 -core's recommendation on how to asynchronously map ds3 data into an st s-1 spe. in this case , the sts-1 spe bi t-format is ex pressed purely in the form of "bit-types" and "numbers of bits within each of these types of bits". if one studies this figure closely he/she will notice that this is the same "87 byte column x 9 row" structure that we have been talking about when defining the sts-1 spe. however, in this figure, the "use r-data" field is now de fined and is said to consist of five (5) different types of bits. each of these bit-types play a role when asynchronously mapping a ds3 signal into an sts-1 spe. each of these types of bits are listed and described below. fixed stuff bits fixed stuff bits are simply "space-filler" bits that simp ly occupy space within the sts-1 spe. these bit-fields have no functional role other than "space occupation". telcordia gr-253-core does not define any particular value that these bits should be set to. each of th e 9 rows, within the sts-1 spe w ill contain 59 of these "fixed stuff" bits. ds3 data bits the ds3 data-bits are (as its name im plies) used to transport the ds3 data -bits within the sts-1 spe. if the sts-1 spe is transporting a framed ds 3 data-stream, then these ds3 data bits will carry both the "ds3 payload data" and the "ds3 overhead bits". each of t he 9 rows, within the sts-1 s pe will contain 621 of these "ds3 data bits". this means that each sts-1 spe contains 5,589 of these ds3 data bit-fields. stuff opportunity bits the "stuff" opportunity bits will functi on as either a "stuff" (or junk) bit, or it will carry a ds3 data-bit. the decision as to whether to have a "stuff opportunity" bit transport a "ds3 data-bit" or a "stuff" bit depends upon the "timing differences" between the ds3 data that is being mapped into the sts-1 spe and the timing source that is driving the sts-1 circuitry within the pte. as will be described later on, these "stuff opportunity" bits play a very important role in "frequency-justifying" the ds3 data that is being mapped into the sts-1 spe. these "stuff opportunity" bits also play a critical role in inducing intrinsic jitter and wander within the ds3 signal (as it is de-mapped by the remote pte). each of the 9 rows, within the sts-1 spe consists of one (1) stuff oppo rtunity bit. hence, there are a total of nine "stuff opportunity" bits within each sts-1 spe. stuff control/indicator bits each of the nine (9) rows within the sts-1 spe contains five (5) stuf f control/indicator bi ts. the purpose of these "stuff control/indicator" bits is to indicate (to the de-mapping pte) whether the "stuff opportunity" bits (that resides in the same ro w) is a "stuff" bit or is carrying a ds3 data bit. if all five of these "stuff control/indicator" bits, within a given row are set to "0", then this means that the corresponding "stuff opportunity" bit (e.g., the "stuff opportunity" bit within the same row) is carrying a ds3 data bit. conversely, if all five of these "stuff control/indicator" bits, within a given row are set to "1" then this means that the corresponding "stuff opportunity" bit is carrying a "stuff" bit. overhead communication bits telcordia gr-253-core permits the user to use thes e two bits (for each row) as some sort of "communications" bit. some mapper devices, such as the xrt94l43 12-channel ds3/e3/sts-1 to sts-12/ stm-1 mapper and the xrt94l33 3-channel ds3/e3/sts-1 to sts-3/stm-1 mapper ic (both from exar corporation) do permit the user to have access to these bit-fields. however, in general, these particular bits can also be th ought of as "fixed stuff" bits, that mostly have a "space occupation" function. 8.2.2 ds3 frequency offsets and the use of the "stuff opportunity" bits in order to fully convey the role that the "stuff-opportunity" bits play, wh en mapping ds3 data into sonet, we will present a detailed discussion of each of th e following "mapping ds3 into sts-1" scenarios. xrt75r12d 96 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer ? the ideal case (e.g., with no frequency offsets) ? the 44.736mbps + 1 ppm case ? the 44.736mhz - 1ppm case throughout ea ch of these cases, we will disc uss how the resulting "bit-stuffi ng" (that was done when mapping the ds3 signal into sonet) affects th e amount of intrinsic jit ter and wander t hat will be present in the ds3 signal, once it is ultimately de-mapped from sonet. 8.2.2.1 the ideal case for mappi ng ds3 data into an sts-1 signal (e.g., with no frequency offsets) let us assume that we are mapping a ds3 signal, wh ich has a bit rate of exac tly 44.736mbps (with no frequency offset) into sonet. furthe r, let us assume that the sonet circ uitry within the pte is clocked at exactly 51.84mhz (also with no frequency offset), as depicted below. given the above-mentioned assumptions, we can state the following. ? the ds3 data-stream has a bit-rate of exactly 44.736mbps ? the pte will create 8000 sts-1 spe's per second ? in order to properly map a ds3 da ta-stream into an sts-1 data-strea m, then each sts-1 spe must carry (44.736mbps/8000 =) 5592 ds3 data bits. is there a problem? according to figure 44 , each sts-1 spe only contains 5589 bits th at are specifically designated for "ds3 data bits". in this case, each sts-1 spe appears to be th ree bits "short". no there is a simple solution no, earlier we mentioned th at each sts-1 spe consists of nine (9) "stu ff opportunity" bits. therefore, these three additional bits (for ds3 data) are obtained by using three of these "stuff opportunity" bits. as a consequence, three (3) of these nine (9) "stuff opportunity" bits, within each sts-1 spe, will carry ds3 data- bits. the remaining six (6) "stu ff opportunity" bits will typi cally function as "stuff" bits. in summary, for the "ideal case"; where there is no fr equency offset between the ds 3 and the sts-1 bit-rates, once this ds3 data-stream has been mapp ed into the sts-1 data-stream, then each and every sts-1 spe will have the following "stuff opportunity" bit utilization. 3 "stuff opportunity" bits will carry ds3 data bits. 6 "stuff opportunity" bits will function as "stuff" bits f igure 45. a s imple i llustration of a ds3 d ata -s tream being m apped into an sts-1 spe, via a pte pte pte 44.736mhz + 0ppm ds3_data_in sts-1_data_out 51.84mhz + 0ppm xrt75r12d 97 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 in this case, this ds3 signal (which has now been mapped into sts-1) w ill be transported across the sonet network. as this sts-1 signal arrive s at the "destination pte", this pte w ill extract (or de-map) this ds3 data- stream from each incoming sts-1 spe. now since each and every st s-1 spe contains exactly 5592 ds3 data bits; then the bit rate of this ds3 signal will be exactly 44.736mbps (such as it was when it was mapped into sonet, at the "source" pte). as a consequence, no "mapping/de-mapping" jitter or wander is induced in the "ideal case". 8.2.2.2 the 44.736mbps + 1ppm case the "above example" was a very ideal case. in reality, there are going to be frequency offsets in both the ds3 and sts-1 signals. for instance bellcore gr-499-c ore mandates that a ds3 signal have a bit rate of 44.736mbps 20ppm. hence, the bit-rate of a "bellcor e" compliant ds3 signal can vary from the exact correct frequency for ds3 by as much of 20ppm in either direct ion. similarly, many sonet applications mandate that sonet equipment use at least a "stratum 3" level clock as its timing source. this requirement mandates that an sts-1 signal must have a bit rate that is in the range of 51.84 4.6ppm. to make matters worse, there are also provisions for sonet equipment to use (what is referred to as) a "s onet minimum clock" (smc) as its timing source. in this case, an sts-1 signal can have a bit-rate in the range of 51.84mbps 20ppm. in order to convey the impa ct that frequency offsets (i n either the ds3 or sts-1 signal) will impose on the bit- stuffing behavior, and the resulting bit-rate, intrinsic jitter and wander within the ds3 signal that is being transported across the sonet network; let us assume that a ds3 signal, with a bit-rate of 44.736mbps + 1ppm is being mapped into an sts-1 signal with a bit-rate of 51.84mbps + 0ppm. in this case, the following things will occur. ? in general, most of the sts-1 spe's will each transport 5592 ds3 data bits. ? however, within a "one-second" perio d, a ds3 signal that has a bit-rate of 44.736mbps + 1 ppm will deliver approximately 44.7 additional bits (over and above that of a ds3 signal with a bit-rate of 44.736mbps + 0 ppm). this means that this particular signal will need to "negative-stuff" or map in an additional ds3 data bit every (1/44.736 =) 22.35ms. in other words, this additional ds3 da ta bit will need to be mapped into about one in every (22.35ms 8 000 =) 178.8 sts-1 spes in order to avoid dropping any ds3 data-bits. what does this mean at the "source" pte? all of this means that as the "source" pte maps this ds 3 signal, with a data rate of 44.736mbps + 1ppm into an sts-1 signal, most of the result ing "outbound" sts-1 spes will transport 5592 ds3 data bits (e.g., 3 stuff opportunity bits will be carrying ds3 data bits, the re maining 6 stuff opportunity bits are "stuff" bits, as in the "ideal" case). however, in approx imately one out of 178.8 "outbound" sts-1 spes, there will be a need to insert an additional ds 3 data bit within this sts-1 spe. whenever this occurs, th en (for these particular sts- 1 spes) the spe will be carrying 5593 ds3 data bits (e.g., 4 stuff opportunity bits will be carrying ds3 data bits, the remaining 5 stuff opportunity bits are "stuff" bits). figure 46 presents an illustration of the st s-1 spe traffic that will be generated by the "source" pte, during this condition. xrt75r12d 98 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer what does this mean at the "destination" pte? in this case, this ds3 signal (which has now been mapped into an sts- 1 data-stream) will be transported across the sonet network. as this sts-1 signal arrives at the "destinati on" pte, this pte will extract (or de- map) this ds3 data from each incoming sts-1 spe. now, in this case most (e.g., 177/178.8) of the incoming sts-1 spes will contain 5592 ds3 data-b its. therefore, the nominal data rate of the ds3 signal being de- mapped from sonet will be 44.736mbps . however, in approximately 1 out of every 178 incoming sts-1 spes, the spe will carry 5593 ds3 data-bits. this means that (during these times) the data rate of the de- mapped ds3 signal will have an instantaneous frequency that is gr eater than 44.736mbps. these "excursion" of the de-mapped ds3 data-rate, from the nominal ds3 frequency can be viewed as occurrences of "mapping/ de-mapping" jitter. since each of these "bit-stuffing" events involve the insertion of one ds3 data bit, we can say that the amplitude of th is "mapping/de-mapping" jitte r is approximately 1ui-pp. from this point on, we will be referring to this type of jitter (e .g., that which is induced by the mapping and de-mapping process) as "de- mapping" jitter. since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35m s, we can state that this jitter has a frequency of 44.7hz. 8.2.2.3 the 44.736mbps - 1ppm case in this case, let us assume that a ds3 signal, with a bi t-rate of 44.736mbps - 1ppm is being mapped into an sts-1 signal with a bit-rate of 51.84mbps + 0ppm. in this case, the follo wing this will occur. ? in general, most of the sts-1 spes w ill each transport 5592 ds3 data bits. ? however, within a "one-sec ond" period a ds3 signal that has a bit- rate of 44.736mbps - 1ppm will deliver approximately 45 too few bits below t hat of a ds3 signal with a bit-rate of 44.736mbps + 0ppm. this means that this particular signal will need to "positive-stuff" or exclude a ds3 data bit from mapping every (1/44.736) = 22.35ms. in other wo rds, we will need to avoid mapping this ds3 data-bit ab out one in every (22.35ms*8000) = 178.8 sts-1 spes. what does this mean at the "source" pte? all of this means that as the "source" pte maps this ds3 signal, with a data rate of 44.736mbps - 1ppm into an sts-1 signal, most of the resultin g "outbound" sts-1 spes will transpor t 5592 ds3 data bits (e.g., 3 stuff opportunity bits will be carrying ds3 da ta bits, the remaining 6 stuff opportunity bits are "stuff" bits). however, in approximately one out of 178.8 "outbound" sts-1 spes, there will be a n eed for a "positive-stuffing" event. f igure 46. a n i llustration of the sts-1 spe traffic that will be generated by the "s ource " pte, when mapping in a ds3 signal that has a bit rate of 44.736m bps + 1 ppm , into an sts-1 signal source pte source pte 44.736mbps + 1ppm 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n spe # n+1 5592 ds3 data bits 5592 ds3 data bits spe # n+177 5593 ds3 data bits 5593 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n+178 spe # n+179 extra ds3 data bit stuffed here sts-1 spe data stream xrt75r12d 99 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 whenever these "positive-stuffing" ev ents occur then (for th ese particular sts-1 spes) the spe will carry only 5591 ds3 data bits (e.g., in this case, only 2 stuff opportunity bits will be carrying ds3 data-bits, and the remaining 7 stuff opportunity bits are "stuff" bits). figure 47 presents an illustration of the st s-1 spe traffic that will be generated by the "source" pte, during this condition. what does this mean at the destination pte? in this case, this ds3 signal (which has now been mapped into an sts- 1 data-stream) will be transported across the sonet network. as this sts-1 signal arrives at the "destinati on" pte, this pte will extract (or de- map) this ds3 data from each incoming sts-1 spe. now, in this case, mo st (e.g., 177/178.8) of the incoming sts-1 spes will contain 5592 ds3 data-b its. therefore, the nominal data rate of the ds3 signal being de- mapped from sonet will be 44.736mbps. however, in approximatel y 1 out of every 178 incoming sts-1 spes, the spe will carry only 5591 ds3 dat a bits. this means that (during t hese times) the data rate of the de- mapped ds3 signal will have an instan taneous frequency th at is less than 44.736mbps . these "excursions" of the de-mapped ds3 data-rate, from the nominal ds3 frequency can be viewed as occurrences of mapping/de- mapping jitter with an amplitude of approximately 1ui-pp. since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7hz. we talked about de-mapping jitter, what about de-mapping wander? the telcordia and bellcore specifications define "wander " as "jitter with a frequency of less than 10hz". based upon this definit ion, the ds3 signal (t hat is being tran sported by sonet) will ce ase to contain jitter and will now contain "wander", whenever th e frequency offset of the ds3 signal being mapped into sonet is less than 0.2ppm. 8.3 jitter/wander due to pointer adjustments in the previous section, we described how a ds3 signal is asynchronously-mapped into sonet, and we also defined "mapping/de-mapping" jitter. in this section, we will describe how occurrences within the sonet network will induce jitter/wander within the ds3 signal that is being tr ansported across the sonet network. in order to accomplish this, we will discuss the following topics in detail. ? the concept of an sts-1 spe pointer f igure 47. a n i llustration of the sts-1 spe traffic that will be generated by the s ource pte, when mapping a ds3 signal that has a bit rate of 44.736m bps - 1 ppm , into an sts-1 signal source pte source pte 44.736mbps - 1ppm 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n spe # n+1 5592 ds3 data bits 5592 ds3 data bits spe # n+177 5591 ds3 data bits 5591 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n+178 spe # n+179 ds3 data bit excluded here sts-1 spe data stream xrt75r12d 100 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer ? the concept of pointer adjustments ? the causes of pointer adjustments ? how pointer adjustments induce jitter/ wander within a ds3 signal being transported by that sonet network. 8.3.1 the concept of an sts-1 spe pointer as mentioned earlier, the sts-1 spe is not aligned to the sts-1 fram e boundaries and is permitted to "float" within the envelope capacity. as a consequence, the sts-1 spe will often time s "straddle" across two consecutive sts-1 frames. figure 48 presents an illustration of an sts-1 spe straddling across two consecutive sts-1 frames. a pte that is receiving and terminating an sts-1 data-stream will perform the following tasks. ? it will acquire and maintain sts- 1 frame synchronization with t he incoming sts- 1 data-stream. ? once the pte has acquired st s-1 frame synchr onization, then it will locate th e j1 byte (e.g., the very byte within the very next sts-1 spe) within the envelope capacity by reading out the contents of the h1 and h2 bytes. the h1 and h2 bytes are referred to (in the sonet standards) as the spe pointer bytes. when these two bytes are concatenated together in order to form a 16-b it word (with the h1 byte functioning as the "most significant byte") then the contents of the "lower" 10 bit-fields (within this 16-bit word) reflects the location of the j1 byte within the en velope capacity of the incoming sts-1 data-stream. figure 49 presents an illustration of the bit format of the h1 and h2 bytes, and indicates which bit-fields are used to reflect the location of the j1 byte. f igure 48. a n i llustration of an sts-1 spe straddling across two consecutive sts-1 frames toh sts-1 frame n sts-1 frame n + 1 j1 byte (1 st byte of spe) j1 byte (1 st byte of next spe) h1, h2 bytes spe can straddle across two sts-1 frames xrt75r12d 101 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 figure 50 relates the contents within these 10 bits (within the h1 and h2 bytes) to the location of the j1 byte (e.g., the very first byte of the sts-1 spe) within the envelope capacity. n otes : 1. if the content of the "pointer bits" is "0x00" then the j1 byte is located immedi ately after the h3 byte, within the envelope capacity. 2. if the contents of the 10-bit expressi on exceed the value of 0x30f (or 782, in decimal format) then it does not contain a valid pointer value. 8.3.2 pointer adjustments within the sonet network the word sonet stands for "synchronous optical ne twork. this name imp lies that the entire sonet network is synchronized to a sing le clock source. however, because the sonet (and sdh) networks can f igure 49. t he b it - format of the 16-b it w ord ( consisting of the h1 and h2 bytes ) with the 10 bits , reflecting the location of the j1 byte , designated f igure 50. t he r elationship between the c ontents of the "p ointer b its " ( e . g ., the 10- bit expression within the h1 and h2 bytes ) and the l ocation of the j1 b yte within the e nvelope c apacity of an sts- 1 f rame x x x x x x x x x x s s n n n n lsb msb h2 byte h1 byte 10 bit pointer expression 521 520 * * * * * * * * * * 436 435 e2 m0 s1 434 433 * * * * * * * * * * 349 348 d12 d11 d10 347 346 * * * * * * * * * * 262 261 d9 d8 d7 260 259 * * * * * * * * * * 175 174 d6 d5 d4 173 172 * * * * * * * * * * 88 87 k2 k1 b2 86 85 * * * * * * * * * * 1 0 h3 h2 h1 782 781 * * * * * * * * * * 697 696 d3 d2 d1 695 694 * * * * * * * * * * 610 609 f1 e1 b1 608 607 * * * * * * * * * * 523 522 c1/j0 a2 a1 toh the pointer value ?0? is immediately after the h3 byte xrt75r12d 102 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer span thousands of miles, traverse many different pieces of equipments, and even cross international boundaries; in practice, the sonet/sdh network is not synchronized to a single clock source. in practice, the sonet/sdh network can be thought of as being divided into numerous "synchronization islands". each of these "synchronization islands" will consist of numerous pi eces of sonet terminal equipment. each of these pieces of sonet terminal equipment will all be synchronized to a single stratum-1 clock source which is the most accurate clock source within the synchronization island. typically a "synchronization island" will consist of a single "timing master" equipment along with multiple "timing slave" pieces of equipment. this "timing master" equipment w ill be directly connected to the stratum-1 clock source and will have the responsibility of di stributing a very ac curate clock sign al (that has been derived from the stratum 1 clock source) to each of the "timing slave" pi eces of equipment within th e "synchronization island". the purpose of this is to permit each of the "timing slav e" pieces of equipment to be "synchronized" with the "timing master" equipment, as well as the stratum 1 clo ck source. typically this "clock distribution" is performed in the form of a bits (building integrated ti ming supply) clock, in whic h a very precise clock signal is provided to the other pieces of equipment via a t1 or e1 line signal. many of these "synchronization islands" will use a stra tum-1" clock source that is derived from gps pulses that are received from satellites that operate at geo-synchronous orbit. other "synchronization islands" will use a stratum-1" clock source that is derived from a very precise local atomic cl ock. as a consequence, different "synchronization islands" will use different stratum 1 clock source s. the up-shot of having these "synchronization islands" that use different "stratum-1 cl ock" sources, is that the stratum 1 clock frequencies, between these "synchronization islands" are likely to be s lightly different from each other. these "frequency- differences" within stratum 1 clock sources will result in "clock-domain changes" as a sonet signal (that is traversing the sonet network) passes from one "synchronization island" to another. the following section will describe how these "frequency differences" w ill cause a phenomen on called "pointer adjustments" to occur in the sonet network. 8.3.3 causes of pointer adjustments the best way to discuss how pointer adjustment events o ccur is to consider an sts-1 signal, which is driven by a timing reference of frequency f1; and that this st s-1 signal is being routed to a network equipment (that resides within a different "synchronization island") and processes sts-1 data at a frequency of f2. n ote : clearly, both frequencies f1 and f2 are at the sts-1 rate (e.g., 51.84mhz). however, these two frequencies are likely to be slightly different from each other. now, since the sts-1 signal (which is of frequency f1 ) is being routed to the network element (which is operating at frequency f2), the typica l design approach for handling "clock-dom ain" differences is to route this sts-1 signal through a "slip buffer" as illustrated below. xrt75r12d 103 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 in the "slip buffer, the "input" sts-1 data (labeled "s ts-1 data_in") is latched in to the fifo, upon a given edge of the corresponding "sts-1 clock_f1" input clock signal. the sts-1 data (labeled "sts-1 data_out") is clocked out of the slip buffer upon a given edge of the "sts-1 clock_f2" input clock signal. the behavior of the data, passing through the "slip buffer" is now described for each possible relationship between frequencies f1 and f2. if f1 = f2 if both frequencies, f1 and f2 are exactly equal, then the sts-1 data w ill be "clocked" into the "slip buffer" at exactly the same rate that it is "clo cked out". in this case, the "slip buffer" will neither fill-up nor become depleted. as a consequence, no pointer-adjustments will o ccur in this sts-1 data stream. in other words, the sts-1 spe will remain at a constant lo cation (or offset) within each sts-1 en velope capacity for the duration that this sts-1 signal is suppor ting this particular service. if f1 < f2 if frequency f1 is less than f2, then this means that the sts-1 data is being "clocked out" of the "slip buffer" at a faster rate than it is being clocke d in. in this case, the "slip buff er" will eventually become depleted. whenever this occurs, a typical strate gy is to "stuff" (or insert) a "dummy byte" into the data stream. the purpose of stuffing this "dummy byte" is to compensa te for the frequency differences between f1 and f2, and attempt to keep the "s lip buffer, at a somewh at constant fill level. n ote : this "dummy byte" does not carry any valuable in formation (not for the user, nor for the system). since this "dummy byte" carries no useful information, it is important that the "receiving pte" be notified anytime this "dummy byte" stuffing occurs. this way, the receiving terminal can "know" not to treat this "dummy byte" as user data. byte-stuffing and pointer incrementing in a sonet network whenever this "byte-stuffing" occurs then the following other things occur within the sts-1 data stream. during the sts-1 frame that contains the "byte-stuffing" event a. the "stuff-byte" will be insert ed into the byte position im mediately after the h3 byte . this insertion of the "dummy byte" immediately after the h3 byte position will caus e the j1 byte (and in-t urn, the rest of the spe) to be "byte-shifted" away from the h3 byte. as a co nsequence, the offset bet ween the h3 byte posi - tion and the sts-1 spe will now ha ve been increa sed by 1 byte. f igure 51. a n i llustration of an sts-1 signal being processed via a s lip b uffer slip buffer slip buffer sts-1 data_in sts-1 clock_f1 sts-1 data_out sts-1 clock_f2 clock domain operating at frequency f1 clock domain operating at frequency f2. xrt75r12d 104 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer b. the "transmitting" network equipment w ill notify the remote terminal of th is byte-stuffing event, by invert - ing certain bits within the "pointer word" (within the h1 and h2 bytes) that are referred to as "i" bits. figure 52 presents an illustration of the bit- format within the 16-bit word (consist of the h1 and h2 bytes) with the "i" bits designated. n ote : at this time the "i" bits are inverted in order to denote t hat an "incrementing" pointer adjustment event is currently occurring. during the sts-1 frame that follows the "byte-stuffing" event the "i" bits (within the "pointer-word" ) will be set back to their normal value; and the contents of the h1 and h2 bytes will be incremented by "1". if f1 > f2 if frequency f1 is greater than f2, then this means that the sts-1 data is being clocked into the "slip buffer" at a faster rate than is being clocked out. in this case, the "slip buffer" will start to fill up. whenever this occurs, a typical strategy is to delete (e.g., negative-stuff) a by te from the slip buffer. the purpose of this "negative- stuffing" is to compensate for the frequency difference s between f1 and f2; and to attempt to keep the "slip buffer" at a somewhat constant fill-level. n ote : this byte, which is being "un-stuffed" does carry valuable information for the user (e.g., this byte is typically a payload byte). therefore, whenever this n egative stuffing occurs, two things must happen. a. the "negative-stuffed" byte must not be simply disca rded. in other words, it must somehow also be transmitted to the remote pte wi th the remainde r of the spe data. b. the remote pte must be notified of the occurrence of these "negative-stuffing" events. further, the remote pte must know where to obt ain this "negative-stuffed" byte. negative-stuffing and pointer-decrementing in a sonet network whenever this "byte negative-stuffin g" occurs then the following other things occur within the sts-1 data- stream. during the sts-1 frame that contains the "negative byte-stuffing" event a. the "negative-stuffed" byte will be inserted into th e h3 byte position. whe never an spe data byte is inserted into the h3 byte position (which is ordinar ily an unused byte), the number of bytes that will exist between the h3 byte and the j1 byte within the very next spe will be reduced by 1 byte. as a consequence, in this case , the j1 byte (and in-tur n, the rest of the spe) will now be "byte-shifted" towards the h3 byte position. f igure 52. a n i llustration of the b it f ormat within the 16- bit word ( consisting of the h1 and h2 bytes ) with the "i" bits designated d i d i d i d i d i s s n n n n lsb msb h2 byte h1 byte 10 bit pointer expression xrt75r12d 105 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 b. the "transmitting" network element will notify the remo te terminal of this "n egative-stuff" event by inverting certain bits within the "pointer word" (within th e h1 and h2 bytes) that are referred to as "d" bits. figure 53 presents an illustration of the bit format within the 16-bit word (consisting of the h1 and h2 bytes) with the "d" bits designated. n ote : at this time the "d" bits are inverted in order to denote that a "decrementing" pointer adjustment event is currently occurring. during the sts-1 frame that follows the "negative byte-stuffing" event the "d" bits (within the pointe r-word) will be set back to their normal va lue; and the contents of the h1 and h2 bytes will be decremented by one. f igure 53. a n i llustration of the b it -f ormat within the 16- bit word ( consisting of the h1 and h2 bytes ) with the "d" bits designated d i d i d i d i d i s s n n n n lsb msb h2 byte h1 byte 10 bit pointer expression xrt75r12d 106 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 8.3.4 why are we talking about pointer adjustments? the overall sonet network consists of numerous "syn chronization islands". as a consequence, whenever a sonet signal is being transmitted fr om one "synchronization island" to another; that sonet signal will undergo a "clock domain" change as it traver ses the network. this clock domain change w ill result in periodic pointer-adjustments occurring within this sonet signal. depending upon th e direction of this "clock-domain" shift that the sonet signal experiences , there will either be periodic "incre menting" pointer-ad justment events or periodic "decrementing" pointer-adjus tment events within this sonet signal. regardless of whether a given sonet signal is experiencing incrementing or decrementing pointer adjustment events, each poin ter adjustment event w ill result in an abrupt 8-bit sh ift in the position of the spe within the sts-1 data-stream. if this sts-1 signal is transporting an "asynchronously-mapped" ds3 signal; then this 8-bit shift in the location of the spe (within the sts-1 signal) will re sult in approximate ly 8uipp of jitter within the asynchronously-mapped ds3 signal, as it is de-mapped from sonet. in ?section 8.5, a review of the category i intrinsic jitter requirements (per telcordia gr-253-core) for ds3 applications? on page 107 we will discuss the "category i in trinsic jitter requirements (for ds 3 applications) per telcordia gr- 253-core. however, for now we will si mply state that this 8uipp of intrin sic jitter far exceeds these "intrinsic jitter" requirements. in summary, pointer-adjustments events are a "fact of lif e" within the sonet/sdh network. further, pointer- adjustment events, within a sonet signal that is tr ansporting an asynchronous ly-mapped ds3 signal, will impose a significant impact on the intrinsic jitter and w ander within that ds3 signal as it is de-mapped from sonet. 8.4 clock gapping jitter in most applications (in which the liu will be used in a sonet de-sync application) the user will typically interface the liu to a mapper device in the manner as presented below in figure 54 . in this application, the mapper ic will have the responsibilit y of receiving an sts- n signal (from the sonet network) and performing all of the following operations on this sts-n signal. ? byte-de-interleaving this incoming sts-n signal into n sts-1 signals ? terminating each of these sts-1 signals ? extracting (or de-mapping) the ds3 signal(s) from the spes within each of these terminated sts-1 signals. f igure 54. i llustration of the t ypical a pplications for the liu in a sonet d e -s ync a pplication ds3 to sts-n mapper/ demapper ic ds3 to sts-n mapper/ demapper ic liu liu sts-n signal tpdata_n input pin tclk_n input de-mapped (gapped) ds3 data and clock xrt75r12d 107 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 in this application, these mapper devices can be thought of as multi-channel devices. for example, an sts-3 mapper can be viewed as a 3-channel ds3/sts-1 to sts-3 mapper ic. similarly, an sts-12 mapper can be viewed as a 12-channel ds3/sts-1 to sts-12 mapper ic. continuing on with this line of thought, if a mapper ic is configured to receive an sts-n signal, and (fro m this sts-n signal) de-map and output n ds3 signals (towards the ds3 facility), then it will typically do so in the following manner. ? in many cases, the ma pper ic will output this ds3 signal, using both a "data-si gnal" and a "clock-signal". in many cases, the mapper ic will output the contents of an entire sts-1 data-stream via the data-signal. ? however, as the mapper ic output this sts- 1 data-stream, it will typically su pply clock pulses (via the clock- signal output) coincident to whenever a ds3 bit is being output via the data-signal. in this case, the mapper ic will not supply a clock pu lse coincident to when a toh, poh, or any "non-ds3 data-bit " is being output via the "data-signal". now, since the mapper ic will output the entire sts-1 data stream (via the data-signal), the output clock- signal will be of the form such that it has a period of 19.3ns (e.g., a 51 .84mhz clock signal). however, the mapper ic will still generate approxim ately 44,736,000 clock pulses during any given one second period. hence, the clock signal that is out put from the mapper ic will be a hor ribly gapped 44.736m hz clock signal. one can view such a clock signal as being a very-jittery 44.736mhz clock signal. this jitter that exists within the "clock-signal" is referred to as "clock-gapping" jitt er. a more detailed discussion on how the user must handle this type of jitter is presented in ?section 8.8.2, recommendations on pre-processing the gapped clocks (from the mapper/asic device) prior to routi ng this ds3 clock and data-signals to the transmit inputs of the liu? on page 119 . 8.5 a review of the category i intrinsic jitter requirements (per telcordia gr-253-core) for ds3 applications the "category i intrinsic jitter requirements" per te lcordia gr-253-core (for ds3 applications) mandates that the user perform a large series of tests against certain specified "scenarios". these "scenarios" and their corresponding requirements is summarized in table 41 , below. t able 41: s ummary of "c ategory i i ntrinsic j itter r equirement per t elcordia gr-253-core, for ds3 applications s cenario d escription s cenario n umber t elcordia gr-253-core c ategory i i ntrinsic j itter r equirements c omments ds3 de-mapping jitter 0.4ui-pp includes effects of de-mapping and clock gapping jit - ter single pointer adjustment a1 0.3ui-pp + ao includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments.note: ao is the amount of intrinsic jitter that was me asured during the "ds3 de- mapping jitter" phase of the test. pointer bursts a2 1.3ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. phase transients a3 1.2ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. 87-3 pattern a4 1.0ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. 87-3 add a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. 87-3 cancel a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. xrt75r12d 108 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer n ote : all of these intrinsic jitter measurements are to be pe rformed using a band-pass filter of 10hz to 400khz. each of the scenarios presented in table 41 , are briefly described below. 8.5.1 ds3 de-mapping jitter ds3 de-mapping jitter is the amount of intrinsic jitter that will be measured within the "line" or "facility-side" ds3 signal, (after it has been de-mapped from a sonet signal) without the occurrence of "pointer adjustments" within the sonet signal. telcordia gr-253-core requires that the "ds3 de-ma pping" jitter be less than 0.4ui-pp, when measured over all possible combinations of ds3 and sts-1 frequency offsets. 8.5.2 single pointer adjustment telcordia gr-253-core states that if each pointer adjustment (within a continuous stream of pointer adjustments) is separated from each other by a period of 30 seconds, or more; then they are sufficiently isolated to be considered "single-pointer adjustments". figure 55 presents an illustration of the "single pointer adjustment" scenario. telcordia gr-253-core states that the intrinsic jitter that is measured (withi n the ds3 signal) that is ultimately de-mapped from a sonet signal that is experiencing "single-pointer adjustment" events, must not exceed the value 0.3ui-pp + ao. n otes : 1. ao is the amount of intrinsic jitter that was measur ed during the "de-mapping" jitter portion of this test. continuous pattern a4 1.0ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. continuous add a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. continuous cancel a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map - ping and pointer adjustments. f igure 55. i llustration of s ingle p ointer a djustment s cenario t able 41: s ummary of "c ategory i i ntrinsic j itter r equirement per t elcordia gr-253-core, for ds3 applications s cenario d escription s cenario n umber t elcordia gr-253-core c ategory i i ntrinsic j itter r equirements c omments initialization cool down measurement period > 30s pointer adjustment events xrt75r12d 109 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 2. testing must be performed for both incrementing and decrementing pointer adjustments. 8.5.3 pointer burst figure 56 presents an illustration of the "pointer burst" pointer adjustm ent scenario per telcordia gr-253- core. telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "burst of po inter adjustment" scenario, must not exceed 1.3ui-pp. 8.5.4 phase transients figure 57 presents an illustration of the "phase transients" pointer ad justment scenario per telcordia gr- 253-core. f igure 56. i llustration of b urst of p ointer a djustment s cenario initialization cool down measurement period > 30s pointer adjustment events 0.5ms t pointer adjustment burst train 0.5ms xrt75r12d 110 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "phase transi ent - pointer adjustment" scenario must not exceed 1.2ui-pp. 8.5.5 87-3 pattern figure 58 presents an illustration of the "87-3 contin uous pattern" pointer adjustment scenario per telcordia gr-253-core. f igure 57. i llustration of "p hase -t ransient " p ointer a djustment s cenario f igure 58. a n i llustration of the 87-3 c ontinuous p ointer a djustment p attern initialization cool down measurement period > 30s pointer adjustment events 0.25s t pointer adjustment burst train 0.25s 0.5s initialization measurement period repeating 87-3 pattern (see below) pointer adjustment events 87-3 pattern 87 pointer adjustment events no pointer adjustments t note: t ranges from 34ms to 10s (req) t ranges from 7.5ms to 34ms (obj) xrt75r12d 111 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 telcordia gr-253-core defines an "87-3 continuous" poin ter adjustment pattern, as a repeating sequence of 90 pointer adjustment events. within this 90 pointer adjustment event, 87 pointer adjustments are actually executed. the remaining 3 pointer adjustments are nev er executed. the spacing between individual pointer adjustment events (within this scenario) can range from 7.5ms to 10seconds. telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "87-3 continu ous" pattern of pointer adju stments, must not exceed 1.0ui-pp. 8.5.6 87-3 add figure 59 presents an illust ration of the "87-3 add pattern" pointer adjustment scenario per telcordia gr-253- core. telcordia gr-253-core defines an "87-3 add" pointer adjustment, as the "87-3 continuous" pointer adjustment pattern, with an additional poin ter adjustment inserted, as shown above in figure 59 . telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "87-3 add" patt ern of pointer adjustments, must not exceed 1.3ui- pp. 8.5.7 87-3 cancel figure 60 presents an illustration of the 87-3 cancel pattern pointer adjustment scenario per telcordia gr- 253-core. f igure 59. i llustration of the 87-3 a dd p ointer a djustment p attern 43 pointer adjustments 43 pointer adjustments added pointer adjustment no pointer adjustments tt xrt75r12d 112 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer telcordia gr-253-core defines an "87-3 cancel" poin ter adjustment, as the "87-3 continuous" pointer adjustment pattern, with an additional pointer adju stment cancelled (or not executed), as shown above in figure 60 . telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "87-3 cancel" pa ttern of pointer adjustments, must not exceed 1.3ui- pp. 8.5.8 continuous pattern figure 61 presents an illustration of the "continuous" pointer adjust ment scenario pe r telcordia gr-253- core. f igure 60. i llustration of 87-3 c ancel p ointer a djustment s cenario f igure 61. i llustration of c ontinuous p eriodic p ointer a djustment s cenario 86 or 87 pointer adjustments no pointer adjustments t cancelled pointer adjustment initialization measurement period repeating continuous pattern (see below) pointer adjustment events t xrt75r12d 113 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 telcordia gr-253-core mandates that the intrinsic jitte r, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "continuous" patte rn of pointer adjustments, must not exceed 1.0ui- pp. the spacing between individual pointer adjustments (within this scenario) can range from 7.5ms to 10s. 8.5.9 continuous add figure 62 presents an illustration of the "contin uous add pattern" pointer adju stment scenario per telcordia gr-253-core. telcordia gr-253-core defines an "c ontinuous add" pointer adjustment, as the "continuous" pointer adjustment pattern, with an additional poin ter adjustment inserted, as shown above in figure 62 . telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "continuous add" pattern of pointer adjustments, must not exceed 1.3ui-pp. 8.5.10 continuous cancel figure 63 presents an illustration of the "continuous cancel pattern" pointer adjustment scenario per telcordia gr-253-core. f igure 62. i llustration of c ontinuous -a dd p ointer a djustment s cenario continuous pointer adjustments continuous pointer adjustments added pointer adjustment tt xrt75r12d 114 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer telcordia gr-253-core defines a "continuous cancel " pointer adjustment, as the "continuous" pointer adjustment pattern, with an additional pointer adju stment cancelled (or not executed), as shown above in figure 63 . telcordia gr-253-core mandates that the intrinsic jitter, within the ds 3 signal that is de-mapped from a sonet signal, which is experiencing the "continuous cancel" pattern of pointer adjustments, must not exceed 1.3ui-pp. 8.6 a review of the ds3 wander requirements per ansi t1.105.03b-1997. to be provided in the next revision of this data sheet. 8.7 a review of the intrinsic jitter and wande r capabilities of the liu in a typical system application the intrinsic jitter and wander test re sults are summarized in this section. 8.7.1 intrinsic jitter test results the intrinsic jitter test results for the liu in ds3 being de-mapped from sonet is summarized below in table 2. f igure 63. i llustration of c ontinuous -c ancel p ointer a djustment s cenario continuous pointer adjustments t cancelled pointer adjustment xrt75r12d 115 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 n otes : 1. a detailed test report on our test procedures and test resu lts is available and can be obtained by contacting your exar sales representative. 2. these test results were obtained via the lius m ounted on our xrt94l43 12-channel ds3/e3/sts-1 mapper evaluation board. 3. these same results apply to sdh/au-3 mapping applications. t able 42: s ummary of "c ategory i i ntrinsic j itter t est r esults " for sonet/ds3 a pplications s cenario d escription s cenario n umber liu i ntrinsic j itter t est r esults t elcordia gr-253-core c ategory i i ntrinsic j itter r equirements ds3 de-mapping jitter 0.13ui-pp 0.4ui-pp single pointer adjustment a1 0.201ui-pp 0.43ui-pp (e.g. 0.13ui-pp + 0.3ui-pp) pointer bursts a2 0.582ui-pp 1.3ui-pp phase transients a3 0.526ui-pp 1.2ui-pp 87-3 pattern a4 0.790ui-pp 1.0ui-pp 87-3 add a5 0.926ui-pp 1.3ui-pp 87-3 cancel a5 0.885ui-pp 1.3ui-pp continuous pattern a4 0.497ui-pp 1.0ui-pp continuous add a5 0.598ui-pp 1.3ui-pp continuous cancel a5 0.589ui-pp 1.3ui-pp xrt75r12d 116 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 8.7.2 wander measurement test results wander measurement test results will be provided in the next revision of the liu data sheet. 8.8 designing with the liu in this section, we will di scuss the following topics. ? how to design with and configure the liu to permit a system to meet the above-mentioned intrinsic jitter and wander requirements. ? how is the liu able to meet the above-mentioned requirements? ? how does the liu permits the user to comply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)? ? how should one configure the liu, if one needs to supp ort "daisy-chain" testing at the end customer's site? 8.8.1 how to design and configure the liu to permit a system to meet the above-mentioned intrinsic jitter and wander requirements as mentioned earlier, in most applic ation (in which the liu will be used in a sonet de-sync application) the user will typically interf ace the liu to a mapper device in the manner as presented below in figure 64 . in this application, the mapper has the responsibility of receiving a sone t sts-n/oc-n signal and extracting as many as n ds3 signals from this signal. as a give n channel within the mapper ic extracts out a given ds3 signal (from sonet) it will typically be applying a clock and data signal to the "transmit input" of the liu ic. figure 64 presents a simple illustration as to how one c hannel, within the liu shou ld be connected to the mapper ic. as mentioned above, the mapper ic will typically output a clock and data signal to the liu. in many cases, the mapper ic will output the contents of an entire sts-1 data-stream via the data signal to the liu. however, the mapper ic typically only supplies a clock pulse vi a the clock signal to the liu coincident to whenever a ds3 bit is being output via the data signal. in this case, the mapper ic would not supply a clock edge coincident to when a toh, poh or any non-ds3 data-bit is being output via the data-signal. figure 64 indicates that the data signal from the mapp er device should be connected to the tpdata_n input pin of the liu ic and that the clock signal from th e mapper device should be connected to the tclk_n input pin of the liu ic. in this application, the liu has the following responsibilities. f igure 64. i llustration of the liu being connected to a m apper ic for sonet d e -s ync a pplications ds3 to sts-n mapper/ demapper ic ds3 to sts-n mapper/ demapper ic liu liu sts-n signal tpdata_n input pin tclk n in p ut de-mapped (gapped) ds3 data and clock xrt75r12d 117 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 ? using a particular clock edge within the "gapped" clock signal (from the mapper ic) to sample and latch the value of each ds3 data-bit that is output from the mapper ic. ? to (through the user of the jitter attenuator block) attenu ate the jitter within this "ds3 data" and "clock signal" that is output from the mapper ic. ? to convert this "smoothed" ds3 data and clock into industry-compliant ds3 pulses, and to output these pulses onto the line. to configure the liu to operate in the correct mode fo r this application, the user must execute the following configuration steps. a. configure the liu to operate in the ds3 mode the user can configure a given channel (within the liu) to operate in the ds3 mode, by executing either of the following steps. ? if the liu has been configured to operate in the host mode the user can accomplish this by setting both bits 2 (e 3_n) and bits 1 (sts-1/ds3*_n), within each of the "channel control registers" to "0" as depicted below. ? if the liu has been configured to operate in the hardware mode the user can accomplish this by pulling all of the fo llowing input pins "low". pin 76 - e3_0 pin 94 - e3_1 pin 85 - e3_2 pin 72 - sts-1/ ds3 _0 pin 98 - sts-1/ ds3 _1 pin 81 - sts-1/ ds3 _2 b. configure the liu to operate in the single-rail mode since the mapper ic will typically output a single "dat a line" and a "clock line" fo r each ds3 signal that it demaps from the incoming sts-n signal, it is imperative to configure each channel within the liu to operate in the single rail mode. the user can accomplish this by executing either of the following steps. ? if the liu has been configured to operate in the host mode the user can accomplish this by setting bit 0 (sr/dr*), within the each of the "chann el control" registers to 1, as illustrated below. channel control register - channel 0 address location = 0x06 channel 1 address location = 0x0e channel 2 address location = 0x16 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused prbs enable ch_n rlb_n llb_n e3_n sts-1/ ds3 _n sr/ dr _n r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 xrt75r12d 118 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer ? if the liu has been configured to operate in the hardware mode then the user should tie pin 65 (sr/dr*) to "high". c. configure each of the channels within the liu to operate in the sonet de-sync mode the user can accomplish this by executing either of the following steps. ? if the liu has been configured to operate in the host mode. then the user should set bit d2 (ja0) to "0" and bit d0 (ja1) to "1", within the jitter attenuator control register, as depicted below. ? if the liu has been configured to operate in the hardware mode then the user should tie pin 44 (ja0) to a logic "high" and pin 42 (ja1) to a logic "low". once the user accomp lishes either of these steps, t hen the jitter attenuator (withi n the liu) will be configured to operate with a very narrow bandwidth. d. configure the jitter attenuator (within each of the channels) to operate in the transmit direction. the user can accomplish this by ex ecuting either the following steps. ? if the liu has been configured to operate in the host mode. then the user should be bit d1 (jatx/jarx*) to "1", wi thin the jitter attenuator control register, as depicted below. channel control register - channel 0 address location = 0x06 channel 1 address location = 0x0e channel 2 address location = 0x16 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused prbs enable ch_n rlb_n llb_n e3_n sts-1/ ds3 _n sr/ dr _n r/o r/o r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 1 jitter attenuator control register - (channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sonet aps recovery time disablech_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 1 xrt75r12d 119 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 ? if the liu has been configured to operate in the hardware mode. then the user should tie pin 43 (jatx/jarx*) to "1". e. enable the "sonet aps recovery time" mode finally, if the user intends to use the liu in an applicat ion that is required to reacquire proper sonet and ds3 traffic, prior within 50ms of an aps (automatic protection switching) even t (per telcordia gr -253-core) , then the user should set bit 4 (sonet aps recovery time disa ble), within the "jitter attenuator control" register, to "0" as depicted below. n otes : 1. the ability to disable the "sonet aps recovery time" mo de is only available if the li u is operating in the host mode. if the liu is operating in th e "hardware" mode, then this "sonet aps recovery time mode" feature will always be enabled. 2. the "sonet aps recovery time" mode will be discussed in greater detail in ?section 8.8.3, how does the liu permit the user to comply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)?? on page 123 . 8.8.2 recommendations on pre-processing the ga pped clocks (from the mapper/asic device) prior to routing this ds3 clock and data-signals to the transmit inputs of the liu in order to minimize the effects of "c lock-gapping" jitter within the ds3 signal that is ultimately transmitted to the ds3 line (or facility), we recomm end that some "pre-proce ssing" of the "data-signa ls" and "clock-signals" (which are output from the mapper device) be implemen ted prior to routing these signals to the "transmit inputs" of the liu. 8.8.2.1 some notes prior to starting this discussion: jitter attenuator control register - channel 0 address location = 0x07 channel 1 ad dress location = 0x0f channel 2 ad dress location = 0x17 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sonet aps recovery time disablech_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 1 1 jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sonet aps recovery time disablech_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 1 xrt75r12d 120 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer our simulation results indicate that jitter attenuator pll (within the li u liu ic) will have no problem handling and processing the "data-signal" and "clock-signal" from a mapper ic/asic if no pre-processing has been performed on these signals. in order words, our simula tion results indicate that the jitter attenuator pll (within the liu ic) will have no proble m handling the "worst-case" of 59 consecutive bits of no clock pulses in the "clock-signal (due to the mapper ic processing the toh bytes, an incrementing pointer-adjustment- induced "stuffed-byte", the poh byte , and the two fixed-stuff bytes with in the sts-1 spe, etc), immediately followed be processing clusters of ds3 data-bits (as shown in figure 44 ) and still comply wi th the "category i intrinsic jitter requirements per telcordia gr-253-core for ds3 applications. n ote : if this sort of "pre-pro cessing" is already supported by the mapper devi ce that you are using, then no further action is required by the user. 8.8.2.2 our pre-processi ng recommendations for the time-being, we recommend that the customer im plement the "pre-processing" of the ds3 "data-signal" and "clock-signal" as described below. currently we are aware that some of the mapper products on the market do implement this exact "pre-processing" algorith m. however, if the customer is implementing their mapper design in an asic or fpga solution, then we strongly recommend that the user implement the necessary logic design to realize the following recommendations. some time ago, we spent some time, studying (and then later testing our solution with) the pm5342 oc-3 to ds3 mapper ic from pmc-sierra. in particular, we want ed to understand the type of "ds3 clock" and "data" signal that this ds3 to oc-3 mapper ic outputs. during this effort, we learned the following. 1. this "ds3 clock" and "data" signal , which is output from the mapper ic consists of two major "repeating" patterns (which we will refer to as "major pattern a" and "major pattern b". the behavior of each of these patterns is presented below. major pattern a major pattern a consists of two "sub " or minor-patterns, (which we w ill refer to as "minor pattern p1 and p2). minor pattern p1 consists of a string of seven (7) cl ock pulses, followed by a single gap (no clock pulse). an illustration of minor pattern p1 is presented below in figure 65 . it should be noted that each of these clock pulses has a period of approximately 19.3ns (or has an "instantaneously frequency of 51.84mhz). minor pattern p2 consists of string of five (5) clock pulses, which is also followed by a single gap (no clock pulse). an illustration of patt ern p2 is pres ented below in figure 66 . f igure 65. i llustration of minor pattern p1 1 2 3 4 5 6 7 missing clock pulse xrt75r12d 121 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 how major pattern a is synthesized major pattern a is created (by the mapper ic) by: ? repeating minor pattern p1 (e.g., 7 clock pulses, followed by a gap) 63 times. ? upon completion of the 63rd transmission of mi nor pattern p1, minor pattern p2 is transmitted repeatedly 36 times. figure 67 presents an illu stration which depicts the procedure that is used to synthesize major pattern a hence, major pattern a consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. these 621 clock pulses were delivered over a period of "(63 x 8) + (36 x 6)" = 720 sts-1 (or 51.84mhz) clock periods. major pattern b major pattern b consists of three sub or minor-patterns (which we w ill refer to as "minor patterns p1, p2 and p3). minor pattern p1, which is used to partially synthesize major pattern b, is exactly the same "minor pattern p1" as was presented above in figure 37 . similarly, the minor pat tern p2, which is also used to partially synthesize major pattern b, is exactly the same "minor pattern p2" as was presented in figure 38 . minor pattern p3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains no gaps. an illustration of minor pattern p3 is pr esented below in figure 68 . f igure 66. i llustration of minor pattern p2 f igure 67. i llustration of p rocedure which is used to s ynthesize major pattern a 1 2 3 4 5 missing clock pulse minor pattern p1 minor pattern p2 repeats 63 times repeats 36 times xrt75r12d 122 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer how major pattern b is synthesized major pattern b is created (by the mapper ic) by: ? repeating minor pattern p1 (e.g., 7 clock pulses, followed by a gap) 63 times. ? upon completion of the 63rd transmission of mi nor pattern p1, minor pattern p2 is transmitted repeatedly 36 times. ? pon completion of the 35th transmission of mino r pattern p2, minor pattern p3 is transmitted once. figure 69 presents an illu stration which depicts the procedure that is used to synthesize major pattern b. hence, major pattern b consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses. these 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 sts-1 (or 51.84mhz) clock periods. putting the patterns together finally, the ds3 to oc-n mapper ic clock output is reproduced by doing the following. ? major pattern a is transmitted two times (repeatedly). ? after the second transmission of major pattern a, major pattern b is transmitted once. ? then the whole process repeats. throughout the re mainder of this document, we will refer to this particular pattern as the "super pattern". figure 70 presents an illustrati on of this "super pattern" whic h is output via the mapper ic. f igure 68. i llustration of minor pattern p3 f igure 69. i llustration of p rocedure which is used to s ynthesize pattern b 1 2 3 4 5 6 pattern p1 pattern p2 repeats 63 times repeats 35 times pattern p3 transmitted 1 time xrt75r12d 123 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 cross-checking our data ? each super pattern consists of (621 + 621 + 622) = 1864 clock pulses. ? the total amount of time, which is required for the "ds3 to oc-n mapper" ic to transmit this super pattern is (720 + 720 + 720) = 2160 "sts-1" clock periods. ? this amount to a period of (2160/51.84mhz) = 41,667ns. ? in a period of 41, 667ns, the liu (w hen configured to operate in the ds3 mode), will output a total (41,667ns x 44,736,000) = 1864 uniformly spaced ds3 clock pulses. ? hence, the number of clock pulses match. applying the super pattern to the liu whenever the liu is config ured to operate in a "sonet de-sync" application, the device will accept a continuous string of the above-defined super pattern, via the tclk input pin (along with the corresponding data ). the channel within the liu (which will be configured to operate in the "ds3" mode) will output a ds3 line signal (to the ds3 fa cility) that complies with the "category i intrinsi c jitter requirements - per telcordia gr-253-core (for ds3 applications ). this scheme is illustrated below in figure 71 . 8.8.3 how does the liu permit the user to co mply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)? telcordia gr-253-core, section 5.3.3.3 mandates that the "aps completion" (or recovery) time be 50ms or less. many of our customers interpret this particular requirement as follows. f igure 70. i llustration of the super pattern which is output via the "oc-n to ds3" m apper ic f igure 71. s imple i llustration of the liu being used in a sonet d e -s ynchronizer " a pplication pattern a pattern a pattern b ds3 to sts-n mapper/ demapper ic ds3 to sts-n mapper/ demapper ic liu liu sts-n signal tpdata_n input pin tclk_n input de-mapped (gapped) ds3 data and clock xrt75r12d 124 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer "from the instant that an aps is init iated on a high-speed sonet signal, all lower-speed sone t traffic (which is being transported via this "high-spee d" sonet signal) must be fully restor ed within 50ms. similarly, if the "high-speed" sonet signal is transporting some pdh signa ls (such as ds1 or ds3, etc.), then those entities that are responsible for acquiring and maintaining ds1 or ds3 frame synchronization (with these ds1 or ds3 data-streams that have been de-mapped from so net) must have re-acquired ds1 or ds3 frame synchronization within 50ms" after aps has been initiated." the liu was designed such that the ds3 signals that it receives from a sonet mapper device and processes will comply with the category i intrinsic jitter requirements per telcordia gr-253-core. reference 1 documents some aps recovery time test ing, which was performed to verify that the jitter attenuator blocks (within the liu) device that permit it to comply with the ca tegory i intrinsic jitter requirements (for ds3 applications) per telcordia gr-2 53-core, do not cause it to fail to comply with the "aps completion time" requirements per section 5.3.3.3 of telcordia gr-253-core. however, table 3 presents a summary of some aps recove ry time requirements that were documented with in this test report. table 3, n ote : the aps completion (or recovery ) time requirement is 50ms. configuring the liu to be able to comply with the sonet aps recovery time requirements of 50ms quite simply, the user can configure a given jitter atte nuator block (associated with a given channel) to (1) comply with the "aps completion time" requirements per telcordia gr-253-core, and (2) also comply with the "category i intrinsic jitter requirements per telcordia gr-253-core (for ds3 applications) by making sure that bit 4 (sonet aps recovery ti me disable ch_n), within the jitter attenuator control register is set to "0" as depicted below. t able 43: m easured aps r ecovery t ime as a function of ds3 ppm offset ds3 ppm o ffset ( per w&g ant-20se) m easured aps r ecovery t ime ( per l ogic a nalyzer ) -99 ppm 1.25ms -40ppm 1.54ms -30 ppm 1.34ms -20 ppm 1.49ms -10 ppm 1.30ms 0 ppm 1.89ms +10 ppm 1.21ms +20 ppm 1.64ms +30 ppm 1.32ms +40 ppm 1.25ms +99 ppm 1.35ms xrt75r12d 125 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 n ote : the user can only disable the "sonet aps recovery time mode " if the liu is operating in the host mode. if the user is operating the liu in the ha rdware mode, then the user will have no ability to disable the "sonet aps recovery time mode" feature. 8.8.4 how should one configure the liu, if one needs to support "daisy-chain" testing at the end customer's site? daisy-chain testing is emerging as a new requirements that many of our customers are imposing on our sonet mapper and liu products. many system designer/manufacturers ar e finding out that whenever their end-customers that are evaluating and testing out their systems (in order to determine if they wish to move forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out these systems with a single piece of test equipment. this means that the end-customer would like to take a single piece of ds3 or sts-1 test equipment and (wit h this test equipment) snake the ds3 or sts-1 traffic (that this test equipment w ill generate) through many or (preferably all) channels within the system. for example, we have had reques t from our customers that (on a system that supports oc-192) our silicon be able to support this ds3 or sts-1 traffic snaking through the 192 ds3 or sts-1 ports within this system. after extensive testing, we have determined that th e best approach to complying with test "daisy-chain" testing requirements, is to configur e the jitter attenuator blocks (within ea ch of the channels within the liu) into the "32-bit" mode. the user can configure the jitter attenuator block (within a gi ven channel of the liu) to operate in this mode by settings in the table below. references 1. test report - automatic protection switching (aps) recover y time testing with the xrt94l43 ds3/e3/sts-1 to sts-12 mapper ic - revision c silicon jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sonet aps recovery time disable ch_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 0 1 1 jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7 b it 6 b it 5 b it 4 b it 3 b it 2 b it 1 b it 0 unused sonet aps recovery time disable ch_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 0 0 0 0 0 1 1 0 xrt75r12d 126 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer 9.0 electrical characteristics n otes : 1. exposure to or operating near the min or max values fo r extended period may cause permanent failure and impair reliability of the device. 2. esd testing method is per mil-std-883d,m-3015.7 3. linear air flow of 200 ft/min recommended for industrial applications. theta ja = 9.4 c/w with 0 lft/min, theta ja = 7.1 c/w with 400lft/min. t able 44: a bsolute m aximum r atings symbol p arameter min max units comments v dd supply voltage -0.5 6.0 v note 1 v in input voltage at any pin -0.5 5.5 v note 1 i in input current at any pin 100 ma note 1 s temp storage temperature -65 150 0 c note 1 a temp ambient operating temperature -40 85 0 c linear airflow 0 ft./min theta ja thermal resistance 7.5 0 c/w linear air flow 200ft/min (see note 3 below) m levl exposure to moisture 5 level eia/jedec jesd22-a112-a esd esd rating 2000 v note 2 t able 45: dc e lectrical c haracteristics : symbol p arameter min . typ . max . units dv dd digital supply voltage 3.135 3.3 3.465 v av dd analog supply voltage 3.135 3.3 3.465 v i cc_ds3 ds3 current consumption using prbs 2 23 -1 pattern 3 1016 1117 ma i cc_ds3ja ds3 current consumption using prbs 2 23 -1 pattern 4 1172 1290 ma i cc_e3 e3 current consumption using prbs 2 23 -1 pattern 3 1040 1140 ma i cc_e3ja e3 current consumption using prbs 2 23 -1 pattern 4 1180 1300 ma i cc_sts1 sts1 current consumption using prbs 2 23 -1 pattern 3 1100 1210 ma i cc_sts1ja sts1 current consumption using prbs 2 23 -1 pattern 4 1300 1430 ma p cc_ds3 ds3 power consumption 5 3.35 3.87 w p cc_ds3ja ds3 power consumption with ji tter attenuator enabled 5 3.87 4.47 w p cc_e3 e3 power consumption 5 3.43 3.95 w p cc_e3ja e3 power consumption with jitter attenuator enabled 5 3.89 4.50 w p cc_sts1 sts1 power consumption 5 3.63 4.19 w xrt75r12d 127 twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 n otes : 1. not applicable for pins with pull-up or pull-down resistors. 2. the digital inputs are ttl 5v compliant. 3. with jitter attenuator disabled. 4. with jitter attenuator enabled. 5. these values are not a measure of power dissipation. these val ues represent the total power consumption. i.e. p cc consumption = p dd dissipation + p ld delivered to load p cc_sts1ja sts1 power consumption with jitter attenuator enabled 5 4.29 4.95 w v il input low voltage 2 0.8 v v ih input high voltage 2 2.0 5.5 v v ol output low voltage, i out = - 4ma 0.4 v v oh output high voltage, i out = 4 ma 2.4 v i l input leakage current 1 10 a c i input capacitance 10 pf c l load capacitance 10 pf t able 45: dc e lectrical c haracteristics : symbol p arameter min . typ . max . units xrt75r12d 128 rev. 1.0.1 twelve channel e3/ds3/sts-1 line interf ace unit with sonet desynchronizer ordering information p art n umber p ackage o perating t emperature r ange xrt75r12dib 420 tbga -40 c to +85 c package dimensions - e 420 tape ball grid array (35 mm x 35 mm, tbga) rev. 1.00 symbol min max min max a 0.051 0.067 1.30 1.70 a1 0.020 0.028 0.50 0.70 a2 0.031 0.039 0.80 1.00 d 1.370 1.386 34.80 35.20 d1 1.5000 bsc 38.10 bsc b 0.024 0.035 0.60 0.90 e 0.0500 bsc 1.27 bsc p 0.006 0.012 0.15 0.30 inches millimeters (a1 corner feature is mfger option) d d1 d d1 1 3 5 7 9 11 13 15 17 19 21 23 25 16 26 20 24 22 18 6 14 12 10 8 4 2 a c e g j l n r u w aa ac ae p af y ad ab v t b h m k f d e a1 feature/mark 129 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and sche dules contained here in ar e only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet december 2006. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xrt75r12d twelve channel e3/ds3/sts-1 line inte rface unit with sonet desynchronizer rev. 1.0.1 revisions r evision d ate c omments p1.0.0 09/22/03 original p1.0.1 10/30/03 added pull-up resistor information for rdy and int . 1.0.0 april 2006 1.added current and power consumption on table 45, ?dc electrical characteristics:,? on page 126 . 2. revised receive monitor enable bit functional description and section 3.3.1 description. 3. updated table 3, ?the alos (analog los) declaration and clearance thresholds for a given setting of reqen (ds3 and sts-1 applications),? on page 23 . 4. minor corrections on transmitter se ction of features summary on page 2. 5. minor typo corrections in sts1clk/12m pin description and in section 1.0 and 4.4 , table 7 and table 9 . 6. added table 2, ?reference clock performa nce specifications,? on page 19. 1.0.1 12/07/06 corrected package thermal resistance specification. |
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